CRII: SHF: A Flexible, Learning-Enabled, and Multi-layer Interconnection Architecture for Optimized On-Chip Communications

技术的快速扩展已经导致每个芯片集成更多数量的核的并行系统的增长。对于当代计算机系统，这一趋势标志着从以计算为中心的设计方法到以通信为中心的设计方法的范式转变。因此，提高片上网络（NoCs）架构的安全性、可靠性、性能和能效被证明是实现未来并行系统性能潜力的最关键的设计挑战之一。尽管现有的片上网络研究已经取得了重大进展，解决个人的设计目标，相对较少的努力，迄今为止，有针对性的所有四个挑战，在一个整体的方式，由于存在的设计权衡和各种片上网络硬件之间的动态交互的复杂性。例如，部署每个路由器的纠错电路可能导致过度延迟和从故障中恢复时的功耗增加。此外，出于安全目的利用区域路由方法可能导致网络热点和拥塞，这极大地阻碍了性能并导致故障。因此，有迫切需要一个优化的片上网络设计，管理动态交互和处理设计权衡。本项目致力于开发一个整体的设计方法，解决整个片上网络的安全性和可靠性，同时最大限度地提高性能和能源效率。为此，该项目首先对NoC故障机制和安全漏洞进行了深入研究。各种安全增强和容错技术的开发和研究，以评估其性能和开销。其次，它开发了一个全面而灵活的片上网络设计框架，集成了多种可重构硬件与嵌入式片上网络增强技术，以保护片上网络免受瞬态和永久性故障和安全漏洞，同时满足功率和性能要求。所设计的框架结合了一个支持学习的控制器，该控制器部署机器学习算法，如监督学习和强化学习，以准确捕获NoC的运行时行为，建模动态交互，并通过自动部署最合适的动态硬件配置来处理权衡，以最大限度地提高系统级安全性，可靠性，功率和性能。最后，该项目开发了一个周期精确的仿真工具和一个FPGA原型来评估所设计的NoC框架。整体设计方法，涵盖了NoC架构设计和机器学习技术，将有利于未来的多核架构，提高安全性，可靠性，能源效率和性能。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

The rapid scaling of technology has led to the growth of parallel systems that integrate an increased number of cores per chip. For contemporary computer systems, this trend has signified a paradigm shift from computation-centric to communication-centric design methodologies. Consequently, enhancing security, reliability, performance, and energy efficiency of Network-on-Chips (NoCs) architectures is proving to be one of the most critical design challenges to realizing the performance potential of future parallel systems. Despite existing NoC research having made significant progress addressing individual design objectives, relatively few efforts to date have targeted all four challenges in a holistic manner due to the existence of design trade-offs and the complexity of dynamic interactions among various NoC hardware. For example, deploying per-router error correction circuit can lead to excessive delays and increased power consumption while recovering from the fault. Additionally, utilizing regional routing methods for security purposes may result in network hotspots and congestion that greatly hinder performance and lead to faults. Therefore, there is an imminent need for an optimized NoC design that manages the dynamic interactions and handles design trade-offs.This project devotes to developing a holistic design methodology that addresses the security and reliability of the entire NoC, while maximizing performance and energy efficiency. To achieve this, the project first carries out a thorough study of NoC fault mechanisms and security vulnerabilities. A variety of security-enhancing and fault-tolerant techniques are developed and investigated in order to assess their performance and overheads. Second, it develops a comprehensive and flexible NoC design framework that integrates multiple reconfigurable hardware with embedded NoC enhancement techniques to protect the NoC from transient and permanent faults and security vulnerabilities while meeting power and performance requirements. The designed framework incorporates a learning-enabled controller that deploys machine learning algorithms, such as supervised learning and reinforcement learning, to accurately capture the runtime behaviors of NoCs, model dynamic interactions, and handle trade-offs by automatically deploying the most suitable configurations of the dynamic hardware with the goal of maximizing system-level security, reliability, power, and performance. Finally, the project develops a cycle-accurate simulation tool and an FPGA prototype to evaluate the designed NoC framework. The holistic design approach, covering the NoC architecture designs and the machine learning techniques, will benefit future multicore architectures with improvements in security, dependability, energy efficiency, and performance.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.