CRII: SHF: A Flexible, Learning-Enabled, and Multi-layer Interconnection Architecture for Optimized On-Chip Communications

CRII:SHF:一种灵活的、支持学习的多层互连架构,用于优化片上通信

基本信息

  • 批准号:
    2245950
  • 负责人:
  • 金额:
    $ 17.47万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2023
  • 资助国家:
    美国
  • 起止时间:
    2023-05-01 至 2025-04-30
  • 项目状态:
    未结题

项目摘要

The rapid scaling of technology has led to the growth of parallel systems that integrate an increased number of cores per chip. For contemporary computer systems, this trend has signified a paradigm shift from computation-centric to communication-centric design methodologies. Consequently, enhancing security, reliability, performance, and energy efficiency of Network-on-Chips (NoCs) architectures is proving to be one of the most critical design challenges to realizing the performance potential of future parallel systems. Despite existing NoC research having made significant progress addressing individual design objectives, relatively few efforts to date have targeted all four challenges in a holistic manner due to the existence of design trade-offs and the complexity of dynamic interactions among various NoC hardware. For example, deploying per-router error correction circuit can lead to excessive delays and increased power consumption while recovering from the fault. Additionally, utilizing regional routing methods for security purposes may result in network hotspots and congestion that greatly hinder performance and lead to faults. Therefore, there is an imminent need for an optimized NoC design that manages the dynamic interactions and handles design trade-offs.This project devotes to developing a holistic design methodology that addresses the security and reliability of the entire NoC, while maximizing performance and energy efficiency. To achieve this, the project first carries out a thorough study of NoC fault mechanisms and security vulnerabilities. A variety of security-enhancing and fault-tolerant techniques are developed and investigated in order to assess their performance and overheads. Second, it develops a comprehensive and flexible NoC design framework that integrates multiple reconfigurable hardware with embedded NoC enhancement techniques to protect the NoC from transient and permanent faults and security vulnerabilities while meeting power and performance requirements. The designed framework incorporates a learning-enabled controller that deploys machine learning algorithms, such as supervised learning and reinforcement learning, to accurately capture the runtime behaviors of NoCs, model dynamic interactions, and handle trade-offs by automatically deploying the most suitable configurations of the dynamic hardware with the goal of maximizing system-level security, reliability, power, and performance. Finally, the project develops a cycle-accurate simulation tool and an FPGA prototype to evaluate the designed NoC framework. The holistic design approach, covering the NoC architecture designs and the machine learning techniques, will benefit future multicore architectures with improvements in security, dependability, energy efficiency, and performance.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
技术的快速扩展导致了并行系统的增长,这些并行系统在每个芯片上集成了更多的核心。对于当代计算机系统来说,这一趋势标志着从以计算为中心的设计方法向以通信为中心的设计方法的范式转变。因此,提高片上网络(NoCs)体系结构的安全性、可靠性、性能和能效是实现未来并行系统性能潜力的最关键的设计挑战之一。尽管现有的NoC研究在解决单个设计目标方面取得了重大进展,但由于存在设计权衡和各种NoC硬件之间动态交互的复杂性,迄今为止针对所有四个挑战的整体努力相对较少。例如,在从故障中恢复时,部署每个路由器的纠错电路可能会导致过长的延迟和增加的功耗。此外,出于安全目的使用区域路由方法可能会导致网络热点和拥塞,从而极大地阻碍性能并导致故障。因此,迫切需要一种优化的NoC设计来管理动态交互并处理设计权衡。该项目致力于开发一种整体设计方法,以解决整个NoC的安全性和可靠性,同时最大化性能和能源效率。为此,该项目首先对NoC故障机制和安全漏洞进行了彻底的研究。开发和研究了各种安全增强和容错技术,以评估它们的性能和管理费用。其次,它开发了一个全面而灵活的NoC设计框架,该框架集成了多种可重构硬件和嵌入式NoC增强技术,在满足功率和性能要求的同时保护NoC免受暂时性和永久性故障以及安全漏洞的影响。设计的框架结合了一个支持学习的控制器,该控制器部署了机器学习算法,如监督学习和强化学习,以准确捕获NoC的运行时行为,对动态交互进行建模,并通过自动部署最合适的动态硬件配置来处理权衡,目标是最大化系统级的安全性、可靠性、功率和性能。最后,本项目开发了一个周期精确的仿真工具和一个FPGA原型来评估所设计的NoC框架。整体设计方法,包括NOC架构设计和机器学习技术,将有利于未来的多核架构,提高安全性、可靠性、能效和性能。该奖项反映了NSF的法定使命,并通过使用基金会的智力优势和更广泛的影响审查标准进行评估,被认为值得支持。

项目成果

期刊论文数量(2)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations
FDMAX:用于求解偏微分方程的弹性加速器架构
Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration
  • DOI:
    10.1109/tsusc.2023.3313880
  • 发表时间:
    2024-03
  • 期刊:
  • 影响因子:
    3.9
  • 作者:
    Ke Wang;Hao Zheng;Jiajun Li;A. Louri
  • 通讯作者:
    Ke Wang;Hao Zheng;Jiajun Li;A. Louri
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Ke Wang其他文献

Diuretic use in incident ESKD: Are we out of the loop?
ESKD 事件中利尿剂的使用:我们是否已脱离困境?
An arc terrane separated from the Yangtze Craton during Rodinia breakup: Insights from Neoproterozoic sedimentary successions of the Erguna Block, Northeast China
罗迪尼亚裂解期间与扬子克拉通分离的弧地体:来自中国东北额尔古纳地块新元古代沉积序列的见解
  • DOI:
    10.1016/j.precamres.2024.107497
  • 发表时间:
    2024
  • 期刊:
  • 影响因子:
    3.8
  • 作者:
    Ke Wang;Yilong Li;Wenjiao Xiao;Haitian Zhang;Guoqing Wang;Jianping Zheng;Xiujuan Bai;Guang Yang;Guohui Zhang;F. Brouwer
  • 通讯作者:
    F. Brouwer
A model of feedback control system on network and its stability analysis
网络反馈控制系统模型及其稳定性分析
A PDE based method for image enhancement
一种基于偏微分方程的图像增强方法
Efficiency measures of the Chinese commercial banking system using an additive two-stage DEA
使用加性两阶段 DEA 衡量中国商业银行体系的效率

Ke Wang的其他文献

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{{ truncateString('Ke Wang', 18)}}的其他基金

Collaborative Research: CSR: Small: Cross-layer learning-based Energy-Efficient and Resilient NoC design for Multicore Systems
协作研究:CSR:小型:基于跨层学习的多核系统节能和弹性 NoC 设计
  • 批准号:
    2321225
  • 财政年份:
    2023
  • 资助金额:
    $ 17.47万
  • 项目类别:
    Standard Grant
CAREER: Mesoscopic Quantum Opto-Electronics in Gate-Defined Transition Metal Dichacogenide Nanostructures
职业:栅极定义的过渡金属二硫族化物纳米结构中的介观量子光电子学
  • 批准号:
    1944498
  • 财政年份:
    2020
  • 资助金额:
    $ 17.47万
  • 项目类别:
    Continuing Grant

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EGFR/GRβ/Shf调控环路在胶质瘤中的作用机制研究
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    81572468
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    2015
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    60.0 万元
  • 项目类别:
    面上项目

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协作研究:SHF:小型:LEGAS:大规模学习演化图
  • 批准号:
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