CRII: SHF: A Flexible, Learning-Enabled, and Multi-layer Interconnection Architecture for Optimized On-Chip Communications

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The rapid scaling of technology has led to the growth of parallel systems that integrate an increased number of cores per chip. For contemporary computer systems, this trend has signified a paradigm shift from computation-centric to communication-centric design methodologies. Consequently, enhancing security, reliability, performance, and energy efficiency of Network-on-Chips (NoCs) architectures is proving to be one of the most critical design challenges to realizing the performance potential of future parallel systems. Despite existing NoC research having made significant progress addressing individual design objectives, relatively few efforts to date have targeted all four challenges in a holistic manner due to the existence of design trade-offs and the complexity of dynamic interactions among various NoC hardware. For example, deploying per-router error correction circuit can lead to excessive delays and increased power consumption while recovering from the fault. Additionally, utilizing regional routing methods for security purposes may result in network hotspots and congestion that greatly hinder performance and lead to faults. Therefore, there is an imminent need for an optimized NoC design that manages the dynamic interactions and handles design trade-offs.This project devotes to developing a holistic design methodology that addresses the security and reliability of the entire NoC, while maximizing performance and energy efficiency. To achieve this, the project first carries out a thorough study of NoC fault mechanisms and security vulnerabilities. A variety of security-enhancing and fault-tolerant techniques are developed and investigated in order to assess their performance and overheads. Second, it develops a comprehensive and flexible NoC design framework that integrates multiple reconfigurable hardware with embedded NoC enhancement techniques to protect the NoC from transient and permanent faults and security vulnerabilities while meeting power and performance requirements. The designed framework incorporates a learning-enabled controller that deploys machine learning algorithms, such as supervised learning and reinforcement learning, to accurately capture the runtime behaviors of NoCs, model dynamic interactions, and handle trade-offs by automatically deploying the most suitable configurations of the dynamic hardware with the goal of maximizing system-level security, reliability, power, and performance. Finally, the project develops a cycle-accurate simulation tool and an FPGA prototype to evaluate the designed NoC framework. The holistic design approach, covering the NoC architecture designs and the machine learning techniques, will benefit future multicore architectures with improvements in security, dependability, energy efficiency, and performance.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.