Synergistic Integration of Novel Superconductor Electronics for Energy-Efficient Computing Accelerators

在这一年里，我们以混合的方式研究了不同超导逻辑族的协整。我们开发了一种用于构建混合AC/DC偏置逻辑电路的标准单元布局架构(10.1109/TASC.2023.3258366)。这种单元布局结构是我们可以非常系统地在同一芯片上通过适当的接口电路将不同的逻辑族组装在一起的基础。接下来，我们开发了一个用于在逻辑族之间交换数据的演示逻辑接口电路(10.1109/TASC.2023.3244147)。与之前的迭代相比，这次更新的设计更加坚固，甚至使用了更现代的制造工艺。然后，我们开发了低延迟混合序列化/反序列化(10.1109/ACCESS.2022.3230447)。这些电路用作元件之间的数据通信以及芯片外传输的设施。这些都是不同逻辑系列之间利用各自优势进行协同集成的极好例子。我们还研究了扩展技术的重要细节，例如信号完整性问题(10.1109/TASC.2023.3239828)和大规模时钟偏差问题(10.1088/13616668/aca3d6)。我们提出了一种用于混合集成的密码处理器的候选体系结构，并展示了高达7 GHz的主要组件。这项工作被选为超导新闻论坛(SNF)2023年3月第52期的专题报道。

In this year we investigated the co-integration of different superconductor logic families in a hybrid manner. We developed a standard cell layout architecture for building hybrid AC/DC-biased logic circuits (10.1109/TASC.2023.3258366). This cell layout architecture is the groundwork in which we can assemble different logic families together on the same chip with appropriate interfacing circuits in a very systematic manner. Next, we developed an demonstrated logic interfacing circuits to exchange data between logic families (10.1109/TASC.2023.3244147). This updated design is more robust compared to previous iterations and even uses a more modern manufacturing process. Then, we developed low-latency hybrid serializers/deserializers (10.1109/ACCESS.2022.3230447). These circuits serve as facilities for data communication between components as well as off-chip transmission. These are excellent examples of synergetic integration between different logic families leveraging their respective strengths. We also looked at important details for scaling up our technology such as issues with signal integrity (10.1109/TASC.2023.3239828) and large-scale clock skew (10.1088/1361-6668/aca3d6). We proposed a candidate architecture for a cryptoprocessor for hybrid integration and demonstrated a major component up to 7 GHz. The work was selected to be featured in Superconductivity News Forum (SNF), Issue No. 52, March 2023.