Performance and Efficiency in HPC with Custom Computing

许多项目已经表明，使用加速器，如现场可编程门阵列（fpga）、多核处理器或图形处理单元（gpu），可以在高性能计算中提供显著的性能和能效优势。尽管如此，加速器的使用并不是普遍的，即使对于很可能从加速器中获利的应用程序领域也是如此。HPC开发人员缓慢采用加速器的原因是多种多样的，例如：缺乏关于加速器的技术知识，不清楚代码优化时间投资的价值主张，缺乏对应用程序优化潜力的理解，缺乏合适的培训材料，缺乏允许将加速器作为黑盒重用的库。我们建议在我们的计算中心建立一个结构化的支持和咨询流程，旨在通过加速计算昂贵的热点，指导HPC开发人员从性能分析和优化潜力估计到最终优化代码的整个过程。这个过程增强了计算科学团队的互补专业知识，从而增加了性能工程任务的价值主张，增加了减少解决方案的时间或能够模拟更大的系统的机会。为了允许开发人员利用以前工作的经验和开发，我们将在可重用库中抽象和封装经常使用的函数。最后，我们将开发适合计算科学和工程开发人员需求的培训材料，并建立演示最佳实践的示例代码存储库。在这个项目中，我们将利用我们的HPC计算中心和我们的用户的具体技术和研究优势。首先，我们利用这样一个事实：我们的核心HPC用户使用自己的和开源代码，并专注于一小部分应用领域（计算纳米光子学、分子动力学、量子化学）。这种对应用领域的关注允许我们共享不同代码的方法和结果。其次，我们将专注于fpga作为加速器技术，因为fpga可以说具有最高的效率潜力，也是一个动态的市场发展。在英特尔收购Altera和IBM CAPI加速器接口的引入之后，fpga的标准化步骤，以及fpga高级设计工具的改进，为fpga在高性能计算领域的更广泛采用提供了新的技术基础。我们相信，我们在FPGA定制计算领域的丰富专业知识和明确的应用重点的结合，将使我们能够显著推进FPGA加速器的高性能计算领域，并通过实际生产的HPC代码展示FPGA的性能和能效优势。

Numerous projects have shown that the use of accelerators, such as field-programmable gate arrays (FPGAs), many-core processors, or graphics processing units (GPUs), can provide significant performance and energy-efficiency benefits in high-performance computing. Still, the use of accelerators is not pervasive, even for application domains that are very likely to profit from accelerators. The reasons for the rather slow adoption of accelerators by HPC developers are manifold, for example: lack of technical knowledge about accelerators, unclear value proposition of time investment in code optimization, missing understanding of the optimization potential for applications, lack of suitable training materials, shortage of libraries that allow for reusing accelerators as black boxes. We propose to establish a structured support and consulting process at our compute center, which aims at guiding HPC developers during the complete process from performance analysis and optimization potential estimation to finally optimizing the code by accelerating computationally expensive hotspots. This process enhances teams from computational sciences with complementary expertise and thus adds a value proposition to the performance engineering task by increasing chances to reduce times-to-solution or being able to simulate larger systems. To allow the developers to leverage the experiences and developments from previous work, we will abstract and encapsulate frequently used functions in reusable libraries. Finally, we will develop training materials that are tailored to the needs of developers from computational science and engineering and establish a repository of example codes that illustrate best practices. In this project, we will exploit the specific technological and research strengths of our HPC computing center and our users. First, we leverage the fact that our core HPC users use own and open-source codes and are focused on a small set of application domains (computational nanophotonics, molecular dynamics, quantum chemistry). This focus in application domains allows us to share methods and results for different codes. Second, we will concentrate on FPGAs as accelerator technology, because FPGAs have arguably the highest efficiency potential and also a dynamic market development. The steps towards standardization after the acquisition of Altera by Intel and the introduction of IBM's CAPI accelerator interface, along with improvements of high-level design tools for FPGAs provide a new technological basis for a broader adoption of FPGAs in HPC. We are confident that the combination of our substantial expertise in the area of custom computing with FPGAs and the clear application focus, will allow us to significantly advance the field for high-performance computing with FPGA accelerators and to demonstrate the performance and energy efficiency benefits of FPGAs with actual production HPC codes.