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Universal Memcomputing in Hardware Realizations of Memristor Cellular Nonlinear Networks

Universal Memcomputing in Hardware Realizations of Memristor Cellular Nonlinear Networks
忆阻器蜂窝非线性网络硬件实现中的通用内存计算
批准号:
441957207
负责人:
Professor Dr. Ricardo Carmona-Galan
金额:
$0.0万
依托单位国家:
德国
项目类别:
Priority Programmes
财政年份:
--
资助国家:
德国
项目状态:
未结题
起止时间:

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中文摘要
翻译
在Mem2CNN第二阶段,我们打算将忆阻器器件及其独特特性扩展到记忆细胞神经网络(m - cnn)中,而不仅仅是目前在细胞状态组件中的应用。该项目的最终目标是探索和实现具有存储可编程性的通用非冯·诺伊曼计算架构的新型硬件,这将实现M-CNN通用机(M-CNNUM)。在提出的系统中,将利用排列在横条中的忆阻器器件来实现M-CNN基因家族,即所谓的染色体。在CNN理论中,染色体是CNN基因的集合,它们以顺序的方式执行各种计算任务,类似于传统计算机系统中观察到的算法操作。忆阻器交叉棒阵列可以用作点积引擎,实现必要的乘法和累加运算来计算每个细胞的偏移量,这类似于相邻细胞的输入和输出的总贡献,以及固定偏差,由每个基因的突触权重加权。然后,我们计划将这种新的基于染色体忆阻器的硬件实现与M-CNN核心的丰富动态相结合,该核心提供本地非易失性存储器和memcomputing能力,以设计整个M-CNNUM单元并演示M-CNNUM指令在我们提出的硬件上的执行。为了促进系统的发展,必须采用混合信号设计技术,利用紧凑和节能的模拟计算核心,并在管理系统运行和数据传输的外围区域配备所需的数字控制电路。该设计将以大规模并行方式执行M-CNNUM操作,以低能量预算要求实现高速通用计算,必须结合CMOS/忆阻器制造电路的所有潜在电路缺陷。此外,它需要为新型M-CNNUM微架构的设计开发创新技术,该微架构类似于这种新型计算机的内部设计和组织。最后但并非最不重要的是,我们设想建立一个软件仿真基础设施,该基础设施将准确描述所提议的M-CNNUM硬件的操作,并将用于演示所提议的M-CNNUM系统在现实任务中的正确操作,例如图像处理应用。以及一个小规模的功能性M-CNNUM阵列的物理实现,用于概念验证,计划。综上所述,Mem2CNN Phase II的主要目标如下:推导出基于交叉棒的M-CNNUM染色体结构;在我们的硬件上演示M-CNNUM指令的操作。3 . M-CNNUM微架构的实现;开发的M-CNNUM实现的概念验证应用。
英文摘要
In Mem2CNN phase II, we intend to expand the incorporation of memristor devices and their unique properties into Memristive Cellular Neural Networks (M-CNNs) beyond their current application solely within the cell state component. The ultimate objective of the proposed project is to explore and implement novel hardware of a universal non-von Neumann computing architecture with stored programmability that will materialize the M-CNN Universal Machine (M-CNNUM). In the proposed system, memristor devices arranged in crossbars will be utilized to implement a M-CNN gene family, the so-called Chromosome. In CNN theory, chromosomes are collections of CNN genes that are executed in a sequential manner to carry out diverse computational tasks, akin to the algorithmic operations observed in traditional computer systems. Memristor crossbar arrays can be utilized as dot-product engines, implementing the necessary multiply-and-accumulate operations for the calculation of each cell’s offset, which resembles the aggregate contribution of neighboring cells’ input, and output, and the fixed bias, weighted by each gene’s synaptic weights. Then, we plan to combine this novel chromosome memristor-based hardware realization with the rich dynamics of the M-CNN core, which offers both local nonvolatile memory and memcomputing capabilities, to design the whole M-CNNUM cell and demonstrate the execution of M-CNNUM instructions on our proposed hardware. In order to facilitate the system development, it is essential to employ mixed-signal design techniques, exploiting the compact and energy-efficient analog computing cores, accompanied by the required digital control circuitry in the peripheral regions that are managing system’s operation and data transfer. This design, which will enable the execution of M-CNNUM operations in a massively parallel manner, achieving high speed universal computation with low energy budget requirements, has to incorporate all the potential circuit imperfections of CMOS/Memristor fabricated circuits. Additionally, it necessitates the development of innovative techniques for the design of the novel M-CNNUM microarchitecture, which resembles the internal design and organization of this novel computer. Last but not least, we envisage the establishment of a software simulation infrastructure that will accurately describe the operation of the proposed M-CNNUM hardware and will be used to demonstrate the proper operation of the proposed M-CNNUM system in real-life tasks, e.g., image processing applications. As well as a physical realization of a small-scale functional M-CNNUM array, for the proof-of-concept, is planned. Summarizing, the main objectives of Mem2CNN Phase II are the following: 1. Derive a crossbar-based M-CNNUM chromosome structure, 2. Demonstrate the operation of M-CNNUM instructions on our hardware, 3. Realization of a M-CNNUM microarchitecture, 4. Proof-of-concept application of the developed M-CNNUM implementation.
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