Study on the Novel Single-Quantum Processing System using Single-Flux-Quantum Logic Circuits
Study on the Novel Single-Quantum Processing System using Single-Flux-Quantum Logic Circuits
批准号:
12450144
负责人:
YOSHIKAWA Nobuyuki
金额:
$9.6万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
2000
资助国家:
日本
项目状态:
已结题
起止时间:
2000 至 2002
中文摘要
单通量量子逻辑电路是利用超导电路中的单通量量子脉冲作为逻辑位信息的一种逻辑电路,与半导体集成电路相比,它具有运行速度快、功耗低的优点,近年来受到广泛关注。由于SFQ电路中的逻辑位信息是用一个SFQ来表示的,而SFQ被认为是一个粒子,所以我们可以用布尔函数来构建一种不同于传统逻辑的新型逻辑运算系统。本研究的目的是利用二元决策图(binary decision diagram, BDD)这一方向图的一种,通过考虑新的SFQ逻辑电路来实现单量子集成系统。在2001年的研究中,我们对BDD SFQ逻辑电路的基本电路单元的电路参数进行了优化,并对其运行进行了验证。2002年,为了构建大规模的BDD SFQ逻辑电路系统,我们设计并实现了微处理器组件,并研究了它们的功能。2003年,我们设计了SFQ微处理器原型,以研究基于异步电路设计方法的大型SFQ电路系统的可行性。设计的SFQ微处理器是具有7条指令的8位位串行微处理器。其目标时钟频率为16ghz。我们已经成功地确认了所有电路元件的正确操作,包括寄存器文件、ALU、程序计数器和控制器。这些结果表明大规模SFQ逻辑电路系统作为下一代高端计算系统的可行性。
英文摘要
Single-flux-quantum (SFQ) logic circuits, which utilize an SFQ pulse in the superconducting circuits as a logical bit information, attract a great deal of attention recently because of their high-speed operating speed and low power dissipation compared with the semiconductor integrated circuits. Because the logical bit information in the SFQ circuits is represented by an SFQ, which is considered as a particle, we may build up a new type of logic operation system different from the conventional logic using me Boolean function.The purpose of this study is to realize a single-quantum integrated system through the consideration of new SFQ logic circuits using a binary decision diagram (BDD), which is one kind of directional graphs.In the research of 2001, we have optimized circuit parameters of the basic circuit cells for the BDD SFQ logic circuits and verified their operations. In 2002 we have designed and implemented the microprocessor components and investigated their functions in order to build a large-scale BDD SFQ logic circuit system. In 2003 we have designed the SFQ microprocessor prototype to investigate the feasibility of a large SFQ circuit system based on the asynchronous circuit design approach. The SFQ microprocessor designed is 8-bit bit-serial microprocessor having seven instructions. Its target clock frequency is 16 GHz. We have successfully confirmed the correct operations in all the circuit components, including register files, an ALU, a program counter and a controller.These results show the feasibility of a large-scale SFQ logic circuit system as a high-end computing system in the next generation.
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吉川信行,森静香,越山潤一: "Verilog HDLによるRSFQ論理回路のタイミング設計手法の検討"電子情報通信学会論文誌C. 7. 643-650 (2000)
Nobuyuki Yoshikawa、Shizuka Mori、Junichi Koshiyama:“使用 Verilog HDL 的 RSFQ 逻辑电路时序设计方法的研究” IEICE Transactions C.7.643-650 (2000)
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J.Koshiyama, N.Yoshikawa: "A Cell-Based Design Approach for RSFQ Circuits Based on Binary Decision Diagram"IEEE Trans. Appl. Superconductivity. Vol.11. 263-266 (2001)
J.Koshiyama、N.Yoshikawa:“基于二元决策图的 RSFQ 电路的基于单元的设计方法”IEEE Trans。
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N.Yoshikawa, J.Koshiyama, K.Motoori, F.Matsuzaki, K.Yoda: "Cell-based top-down design methodology for RSFQ digital circuits"Physica C. 357-360. 1529-1539 (2001)
N.Yoshikawa、J.Koshiyama、K.Motoori、F.Matsuzaki、K.Yoda:“RSFQ 数字电路的基于单元的自顶向下设计方法”Physica C. 357-360。
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K.Fujiwara, H.Hoshina, J.Koshiyama, N.Yoshikawa: "Design and Component Test of RSFQ Packet Decoders for Shift Register Memories"Physica C. 378-381. 1475-1480 (2002)
K.Fujiwara、H.Hoshina、J.Koshiyama、N.Yoshikawa:“移位寄存器存储器的 RSFQ 数据包解码器的设计和组件测试”Physica C. 378-381。
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N. Yoshikawa and J. Koshiyama: "Top-Down RSFQ Logic Design Based on a Binary Decision Diagram"IEEE Trans. Appl. Superconductivity. 11. 1098-1101 (2001)
N. Yoshikawa 和 J. Koshiyama:“基于二元决策图的自顶向下 RSFQ 逻辑设计”IEEE Trans。
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