Evaluation of Asynchronous Hardware in terms of Resistivity against Cryptographic Attacks and Optimum Implementation of IPSecurity

对被称为DPA(Differential Power Attack)的密码系统的攻击，使得它们能够通过观察执行加解密过程中功耗的时间相关性来解密系统的秘密信息，这对使用密钥的安全性构成了严重的威胁。对于硬件设计，已知其中不使用唯一全局时钟的异步方法。在异步设备中，处理时间根据操作和数据的类型而有所不同。因此，异步设计的密码体制有望对DPA具有很高的抵抗力。本研究的目的是低成本、高性能地实现这样一种禁止解密密钥的安全处理。它在现实世界中的应用是另一个目标。本研究取得的成果总结如下：1.开发密码系统的DPA电阻率评估方法：为了设计安全的密码设备，在DESI…的每个阶段评估抵抗攻击的能力需要更多的GN从前端流向后端。对于前端设计，我们提出了一种算法级的高速仿真方法，并对其进行了评估。2.低开销高速低成本异步设备的设计：提出并实现了一种新的数据捆绑异步电路握手协议，该协议可以使用与同步电路相同的数据路径。该协议有效地产生了阶段延迟。评估实验表明，实现该协议的电路比传统设计的电路具有更低的功耗和更高的速度。3.提出了有效的DPA攻击和对策：以DES为例，通过合理选择参考位置和参考比特以及对采样数据进行随机处理的方法，提出了有效的DPA攻击。我们还提出了一种将随机变量引入加密表的方法，称为随机切换表(RST)。RST算法适用于具有宏存储器的密码系统，具有很高的实际应用价值。将RST用于数据路径的捆绑数据异步电路有望在速度、功耗和安全性方面全面提高。4.评估VPN(虚拟专用网)作为安全协议的应用的性能：以OpenVPN为代表，对开源VPN软件进行性能评估。结果表明，缓存会成为VPN软件实现的瓶颈。在此类应用中，专用硬件将是有效的，具有DPA电阻率的硬件密码体制将提高安全性，这属于未来的工作。该研究成果已发表在29篇论文中(2篇日本期刊，4篇英文期刊，5篇国际会议论文集，18篇国内会议论文集)。根据相关研究成果进行了专利申请。较少

Attacks to cryptosystems called DPAs (Differential Power Attacks) that enable them to decode the secret information of the systems by observing time dependence of power consumption during executing encryption and decryption processes pose a serious treat to security using secret keys. For hardware design, asynchronous methodology is known in which a unique global clock is not used. In asynchronous devices, processing time varies according to types of operations and data. Thus the asynchronously designed cryptosystems are expected to have high resistivity against DPA. This study was aimed at realization of such security processing that disables decoding secret keys at low cost and with high performance. Its application to real world is another objective. Results achieved by this study are summarized as follows.1.Developing methodology to evaluate DPA resistivity of cryptosystems : For designing secure cryptographic devices, evaluation of resistivity against attacks at each stage of desi … More gn flow from front to back ends are needed. For front-end design we proposed and evaluated a high speed simulation method at algorithmic level. We found that for back-end design circuit simulations are effective.2.Designing high speed and low cost asynchronous devices with low overhead : A new handshake protocol for bundled-data asynchronous circuits which can use the same data paths as those designed for synchronous circuits was proposed and implemented. The protocol generates efficiently stage delays. Evaluation experiments revealed that circuits implementing the protocol have lower power consumption and higher speed than conventional design.3.Proposing effective DPA attacks and developing the countermeasures : Taking DES as an example, we proposed effective DPA attacks by properly selecting reference positions and bits as well as stochastic methods to process the sampled data. We also proposed a method to introduce random variables to encryption table called RST (Random Switching Table). RST is applicable to cryptosystems with macro memory in FPGA, and thus valuable in many real applications. Bundled-data asynchronous circuits with RST for data paths are expected to improve all aspects of speed, power consumption, and security.4.Evaluating performance of VPN (Virtual Private Network) as an application of security protocol : We focused on OpenVPN as a representative of open source VPN software and evaluated the performance. Results showed that cache can form a bottleneck in software implementation of VPN. In such applications, dedicated hardware will be effective, and hardware cryptosystems with DPA resistivity will increase the degree of security, which belong to future work.Achievements of the research have been published in 29 articles (2 Japanese journals, 4 English journals, 5 international conference proceedings, and 18 domestic conference proceedings). An application of patent was made based on results from related study. Less