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Research on a Very Large Data Path processor

Research on a Very Large Data Path processor
超大型数据路径处理器的研究
批准号:
07458052
负责人:
TANAKA Hidehiko
金额:
$4.35万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
1995
资助国家:
日本
项目状态:
已结题
起止时间:
1995 至 1997

项目摘要

项目成果

TANAKA Hidehiko的其他基金

相关文献

中文摘要
翻译
在这项研究中,我们仔细研究了并行性提取、控制依赖处理和增强存储系统,这些都可能是超大数据路径(VLDP)体系结构的关键技术。研究结果如下:首先,我们考察了控制依赖和数据依赖对并行性的制约:我们发现,当我们同时拥有完美的分支预测器和完整的存储系统时,VLDP体系结构的性能可以达到传统标量处理器的几十倍;其次,我们研究了适合VLDP体系结构的分支处理。这种分支处理需要同时处理多个控制流,并且需要跨多个分支推测性地获取指令。为此,我们提出了一种新的分支预测器--多级分支预测器,并对其性能进行了测试;再次,利用新提出的基于线性函数求值预测引用地址的数据预取算法,对基于缓存机制的存储系统进行了改进。我们证实了这个新系统减少了内存引用的开销。此外,我们还检查了内存和数据路径之间的流量,这往往是高性能处理器的瓶颈。实验结果表明,当VLDP体系结构利用数量可观的ALU之间的直接数据传输时,VLDP体系结构的流量将减少到传统方案的一半以下,从而明确了VLDP体系结构的技术问题,并证实了性能改进的可能性。
英文摘要
In this research, we took a close look at parallelism extraction, handling of control dependencies, and enhanced memory system, which could be the key technologies of Very Large Data Path (VLDP) architecture. The outcome we gained are as follows.Firstly, we examined the characteristics of parallelism restricted by control dependencies and data dependencies : we found that the VLDP architecture can achieve dozens of times as much performance as conventional scalar processors can, when we have both the perfect branch predictor and the complete memory system.Secondly, we examined suitable branch handling for the VLDP architecture. This branch handling needs to treat simultaneously plural control flow and needs to fetch instructions speculatively across many branches. For this purpose, we proposed a new branch predictor named multi-level branch predictor and examined its behavior.Thirdly, we improved a memory system based on the cache mechanism by utilizing a newly proposed data prefetch algorithm that predicts a referenced address based on the evaluation of a linear function. We confirmed this new system lessens overhead of memory references. Moreover we examined the traffic between the memory and the datapath, which tends to be a bottleneck for high performance processors. We showed that this traffic is reduced to less than half of conventional scheme when the VLDP architecture utilizes the direct data transfer among the remarkable number of ALUs.From these results, technological issues of VLDP architecture are made clear and we confirmed the possibility of performance improvement.
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  • 资助金额:
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