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New Design and Implementation of On Senson Compression

New Design and Implementation of On Senson Compression
On Senson 压缩的新设计和实现
批准号:
07555117
负责人:
AIZAWA Kiyoharu
金额:
$4.8万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (A)
财政年份:
1995
资助国家:
日本
项目状态:
已结题
起止时间:
1995 至 1996

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中文摘要
翻译
在这项研究中,我们提出了一种新颖的图像传感器,它可以压缩图像信号,因为利用图像信号的并行性在成像器平面上压缩图像信号,可以显著减少从成像器读出的信号的量。因此,该传感器可以潜在地应用于对成像速度和分辨率要求很高的实时成像的高像素率相机和处理系统,而很高的带宽是这些高像素率传感器和处理系统可行性的根本限制。研究了下面列出的两种压缩传感器的结构。基于这两种方法的原型运行速度都超过了1000帧/秒。(1)像素并行体系结构实现了所需的所有计算元素,包括检测、码率控制和地址编码。测试了一个32×32像素的VLSI原型。(2)列并行结构为了提高填充因子和功耗,研究了一种列并行结构。实现了一个32×32像素的VLSI原型,显示了良好的PITURES质量。
英文摘要
In this research, we propose a novel image sensor on which image signal can be compressed Since image single is compressed on the imager plane by making use of parallel nature of image signals, the amount of sigual read out from the imager can be significantly reduced. Thus, the proposed sensor can be potentially applied to high pixel rate cameras and processing systems which require very high speed imaging and very high resolution for real time imaging ; the very high bandwidth is the fundamental limitation for feasibility of those high pixel rate sensors and processing systems.Conditional replenishment algorithm is employed for the compression scheme ; it detects temporally changing pixels as active pixels and output those active pixels. Two architechtures of compression sensors listed below were investigated. The prototypes based on both approaches operate more than 1000 frames per second.(1) Pixel Parallel ArchitectureAll the required computational elements, that are detection, rate control and address encoding, were implemented. A prototype VLSI which has 32 x 32 pixels was examined.(2) Column Parallel ArchitectureIn order to improve fill factor and power dissipation, a column parallel architecture were investigated. A prototype VLSI which has 32 x 32 pixels was implemented and shows good quality of pitures.
期刊论文(40)
专著(0)
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会议论文
K.Aizawa: "On Sensor Image Compression based on Pixel Parallel and Column Parallel Architectures" IEEE Int.Symp on Circuit and Systems. IV. 179-181 (1996)
K.Aizawa:“基于像素并行和列并行架构的传感器图像压缩”IEEE Int.Symp on Circuit and Systems。
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通讯作者:
K.Aizawa, H.Ohno, Y.Egi, T.Hamamoto, M.Hatori et al.: "New design and implementation of on sensor compression chip based on pixel parallel architecture" The Journal of the Institute of Image Information and Television Engineers of Japan. 51,2. 270-273 (19
K.Aizawa、H.Ohno、Y.Egi、T.Hamamoto、M.Hatori 等人:“基于像素并行架构的传感器压缩芯片的新设计与实现”图像信息与电视工程师学会学报
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K.Aizawa,Y,Egi,T.Hamamoto,M.Hatori,J.Yamazaki: "An Image Sensor for on sensor compression" Computer Architecture For Machine Perception. 14-20 (1995)
K.Aizawa、Y、Egi、T.Hamamoto、M.Hatori、J.Yamazaki:“用于传感器压缩的图像传感器”机器感知计算机体系结构。
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浜本: "動き適応イメージセンサ" 映像情報メディア学会誌. 51・2. 277-279 (1997)
滨本:“运动自适应图像传感器”图像信息和电视工程师学会杂志51・279(1997)。
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共 40 条
    Lifelog Infrastructure : Capture, Processing, Sharing
    • 批准号:
      20240011
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $22.55万
    • 财政年份:
      2008
    • 负责人:
      AIZAWA Kiyoharu
    • 依托单位:
    Functional Surveillance System Capturing Wide-Angle and Close-Up Views
    • 批准号:
      17300056
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $5.06万
    • 财政年份:
      2005
    • 负责人:
      AIZAWA Kiyoharu
    • 依托单位:
    Summarization and Indexing of Home and Wearable Video
    • 批准号:
      15360201
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $5.12万
    • 财政年份:
      2003
    • 负责人:
      AIZAWA Kiyoharu
    • 依托单位:
    Multi-focus image processing for visual effect generations
    • 批准号:
      13450150
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $6.53万
    • 财政年份:
      2001
    • 负责人:
      AIZAWA Kiyoharu
    • 依托单位:
    海外基金