Development of Coarse-Grained Dynamic Self-Reconfigurable Device aiming for Reduction of Reconfiguration Overhead

在本项目中，我们研究了基于线逻辑的动态自重构的大规模并行处理机器——粗粒度塑料细胞架构（PCA），以期通过减少重构开销，在实际应用中实现显著的性能提升。我们开发了一个动态自重构体系结构的仿真平台。我们的平台使我们能够定量分析性能与架构参数之间的关系，包括操作粒度、重新配置粒度、数据总线带宽、重新配置带宽和内存密度。我们已经用这个平台做了一些案例研究。我们还开发了一个自动合成工具，涵盖了各种不同粒度参数的自重构设备。在给定C语言设计的情况下，我们的工具执行从操作资源分配到放置和路由的综合流程。我们还对架构进行了一些评估……更多地使用我们的工具。在实验的基础上，我们设计并制作了一个动态自重构架构的原型芯片。尽管基于alu的粗粒度可重构设备适用于逐字处理，但我们注意到它们不能有效地用于具有复杂控件的顺序处理。因此，我们开发了一种具有双alu阵列/RISC处理器工作模式能力的架构，通过根据目标应用的特点改变器件的工作模式来实现性能增强。我们还应该注意到，可重构设备比asic更容易受到软错误的影响，因为需要配置大量的SRAM。为了克服这一缺点，我们研究了一种动态可重构的软错误自动诊断和修复体系结构。从这三年的研究中，我们获得了一些关于动态自重构的粗粒度体系结构的关键思想和有价值的知识，并对它们的优点进行了展望。少

In this project, we have studied on coarse-grained Plastic Cell Architecture (PCA), a dynamically self-reconfigurable massively-parallel processing machine based on wired-logic, in order to achieve drastic performance enhancement with practical applications by reducing reconfiguration overhead.We have developed a simulation platform for dynamically self-reconfigurable architectures. Our platform enables us to make a quantitative analysis of relations between performance and the architecture parameters including operation granularity, reconfiguration granularity, data-bus bandwidth, reconfiguration bandwidth, and memory density. We have made some case studies using the platform. We have also developed an automated synthesis tool which covers various self-reconfigurable devices of different granularity parameters. Given a design in C language, our tool performs synthesis flow from operation resource allocation to placement and routing. We have also made some evaluations of architectures … More using our tool.Based on the experiments so far, we have designed and fabricated a prototype chip of the proposed dynamically self-reconfigurable architecture. Although ALU-based coarse-grained reconfigurable devices are suitable for word-wise processing, we noticed that they are not efficiently used for sequential processing with complicated controls. Thus, we have developed an architecture which has dual ALU-array/RISC processor operating mode capability to achieve performance enhancement by changing operating mode of the device according to characteristics of target applications.We should also notice that reconfigurable devices are more vulnerable to soft-errors than ASICs, because of large amount of SRAM for configuration. To overcome this disadvantage, we have studied on a dynamically reconfigurable architecture that diagnoses and repairs autonomously the soft-errors.From our research in these three years described so far, we have acquired several key ideas and valuable knowledge on dynamically self-reconfigurable coarse-grained architectures, and clarified a prospect of showing their merits. Less