A Study on a multi-processor for multi-resolution processing in mobile applications

在未来，通过移动的终端上的相机收集视频信息变得流行，因为相机模块变得便宜。然而，通过相机的原始数据通常是低SNR的，并且其中在实际使用之前需要大量处理。本计画的研究目标是利用多分辨率处理来减少原始资料的处理量，并建立一个处理器架构，在低功率消耗下，可达到TOPS（伊拉运算每秒）的处理能力，并具有可程式化的能力来实现各种应用。对于原始数据处理，通过使用多分辨率来评估颜色增强和前景分离算法以减少处理量。彩色图像增强采用HSI颜色系统中H的单个颜色元素，并采用小波变换进一步减少到113。在沃尔什谱域上使用由细到粗的处理的前景分离变得稳定，并且将处理量减少到仅为原始处理量的10%。这两种算法都采用逐像素处理，包括许多条件跳转指令，处理器的流水线控制是不合适的，因为在JUMP指令之后有许多NOP操作。因此，超并行DSP的方法，不采用流水线控制在每个元素处理器建立了为此目的。新采用的分段总线在块式空间操作中工作得很好，并且已经表明，分段总线方法在全搜索运动补偿方面优于Sysplane方法。为了减少芯片：在非流水线控制下，时钟频率设置为最高。作为初步的硬件评估，FPGA实现了单片FPGA可以容纳96个80年代中期的DSP，相当于50K门数。一个1000K的门系统将达到280GOPS。

In future, video information gathering through a camera on a mobile terminals becomes popular because camera modules become cheap. Howeve4 raw data through cameras are generally low SNR, and, therein, requires a lot of processing before actual use. The research target in this project consists of processing amount reduction for raw data handling by use of multi-resolution processing and the processor architecture establishment, which can wale up to TOPS (Ira Operations Per Second) processing capabffity under low power dissipation, with programmable capability for realizing a variety of applications. For raw data handling, color enhancement and foreground separation algorithms are evaluated for processing amount reduction by using multi-resolution. The color image enhancement uses single color element of H in the HSI color system, and it also employs wavelet transform for further reduction to 113. Foreground separation, using fine-to-coarse processing on Walsh spectrum domain, becomes stable and reduces the processing amount to only 10% of the original one. Both algorithms employs pixel wise processing including many conditional jump instructions, pipeline control of processors are not suitable, because of many NOP operations after JUMP instructions. As a result, a super-parallel DSP approach which does not employ pipeline control in every element processor is established for this purpose. The newly employed segment buses works quite well in block wise spatial operations, and it has been shown that segment bus approach is better than Systolic approach in terms of full search motion compensation. In order to reduce chip : sire, the clock frequency employed is set to the highest one under non-pipeline control As a preliminary hardware evaluation, FPGA implementation has been carried out and a single FPGAcan hold 96 DSPs of mid 1980s, resulting 50K gate count equivalently. A 1000K gate system will reach 280GOPS.