Design of a logic circuit for finite differencing of Navier-Stokes equations

本研究作为计算流体力学（CFD）的一种创新的计算方法，为了获得高性能和节省使用计算的计算机的电力，在现场可编程门阵列（FPGA）器件上设计了一种基于分数步法求解Navier-Stokes方程的有限差分逻辑电路，该逻辑电路可以重复构建。

In this study as an innovative computational method for computational fluid dynamics (CFD)to obtain the high performance and to save the electric power of computers which use the computation, a logic circuit of finite difference based on the fractional-step method solving Navier-Stokes equations was designed on the field-programmable gate array (FPGA)device in which the logic circuit can be repeatedly constructed.