PACIFIC - Photonic Accelerator ChIp For InferenCe

我们开发了第一个用于人工智能（AI）推理的大规模并行光子加速器芯片。我们的方法是新颖的：光的幅度调制，结合密集波分复用（DWDM）。与其他解决方案相比，这种组合将更多的计算线程挤压到光束中。幅度调制还可以最大限度地减少信号损失，使我们能够进一步扩展。因此，我们不仅可以超越竞争对手的张量处理单元;我们还可以缩小当前性能和市场需求之间的差距，并（至关重要的是）继续扩展以满足未来的需求。我们的芯片针对最广泛使用和计算密集型的AI任务进行了优化：矩阵向量乘法（MVM）运算。通过在标准互补金属氧化物半导体（CMOS）芯片上使用光子学，我们可以实现最高的计算密度，远远高于标准CMOS电子器件。50 x50矩阵可在150 mm 2上实现每秒1 Peta操作（POPS）。

We have developed the first massively parallel photonic accelerator chip for artificial intelligence (AI) inference. Our approach is novel: amplitude modulation of light, combined with Dense Wavelength Division Multiplexing (DWDM). This combination squeezes many more computing threads into a light beam, compared to alternative solutions. Amplitude modulation also minimises signal losses, allowing us to scale even further. As a result, we can not only outperform rival tensor processing units; we can also close the gap between current performance and market need, and (crucially) continue scaling to meet future needs. Our chip is optimised for the most widely used and compute-intensive AI task: Matrix Vector Multiplication (MVM) operations. By using photonics on a standard Complementary Metal Oxide Semiconductor (CMOS) chip, we can achieve the highest possible compute density, far higher than standard CMOS electronics. A 50x50 matrix enables 1 Peta Operations Per Second (POPS) on 150 mm2.