High throughput asynchronous digital logic implementation flow

所有现代数字半导体，也称为集成电路（IC），都是使用晶体管制成的逻辑门构建的，并使用时钟信号将数据“同步”馈送到处理管道中。当一台笔记本电脑在市场上被称为3Ghz Intel Pentium时，这表明主CPU使用以3Ghz运行的内部时钟来驱动其数据管道。时钟越快，在给定时间内可以处理的数据就越多，从而为IC和笔记本电脑提供性能。半导体工艺进展（最先进的现在下降到5 nm及以下），已经允许每平方毫米硅制造更多的栅极，创造越来越大的器件，并且时钟速度从20世纪70年代早期的100 Hz急剧增加到目前领先设计的~3GHz的标准。复杂的时钟网络（时钟树）被迫以越来越快的速度运行-消耗IC的大部分功率并成为IC性能的限制因素。为了缓解这些问题，在过去的15年中，引入了多时钟域、时钟门控和变速时钟等设计技术，增加了相当大的设计复杂性。这些创新现在已经失去了动力，时钟被认为是高性能IC设计的限制因素。Platipus的“BroadPipe”技术通过采用正在申请专利的创新无时钟设计架构，消除了对越来越快的时钟的需求，从而突破了这一性能障碍。与以前尝试转向无时钟架构不同，BroadPipe技术正在开发，以与行业标准EDA工具兼容。为了证明这些概念，现场可编程门阵列（FPGA）IC的BroadPipe原型实现将在未来12个月内向领先的客户展示。为了更广泛地采用这一世界领先的技术，Platipus正在寻求使用行业标准工具创建全自动设计流程。我们的赠款申请将资助这种自动化流程的开发，并允许我们对潜在的目标市场，客户，合作伙伴和竞争对手进行市场研究。这是公司发展的关键一步，将开辟新的应用程序，新颖的商业模式和收入来源，并为我们提供大量资金以加速其增长做好准备。

All modern digital semiconductors, also known as integrated circuits (ICs), are built using logic gates made of transistors and use a clock signal to 'synchronously' feed data into a processing pipeline. When a laptop is marketed as having a 3Ghz Intel Pentium, this indicates that the main CPU uses an internal clock running at 3Ghz to drive its data pipeline. The faster the clock, the more data can be processed in a given time, giving the IC, and hence your laptop, its performance. Advances in semiconductor processes (with the most advanced now going down to 5nm and below), have allowed more gates to be manufactured per mm2 of silicon, creating larger and larger devices, and the dramatic increases in clock speeds from 100s of Hz in the early 1970s to the current norms of ~3GHz for leading designs.However, these large ICs with billions of transistors have led to large, complicated clock networks (clock trees) being forced to run at faster and faster speeds - both consuming a high proportion of the IC's power and becoming the limiting factor for the IC's performance. To mitigate these issues design techniques such as multiple clock domains, clock gating and variable speed clocks have been introduced over the last 15 years - adding considerable design complexity. These innovations are now running out of steam and clocks are recognized as the limiting factor for high performance IC design.Platipus' "BroadPipe" technology smashes through this performance barrier by employing an innovative patent pending clockless design architecture, removing the need for faster and faster clocks. Unlike previous attempts to move to a clockless architecture, BroadPipe technology is being developed to be compatible with industry standard EDA tools. To prove these concepts, a BroadPipe prototype implementation of a Field Programmable Gate Array (FPGA) IC will be demonstrated to lead customers over the next 12 months.To allow wider adoption of this world beating technology, Platipus is looking to create a fully automated design flow using industry standard tools. Our grant application will fund the development of this automated flow, as well as allowing us to conduct market research on potential target markets, customer, partners and competitors. This is a critical step in the development of the company and will open-up new applications, novel business models and revenue streams, and prepare us for significant funding to accelerate its growth.