Optimization of Massively Parallel Stochastic Simulations

非传统架构已经显示出大量的节能效果，并显著提升了一系列领域中许多应用程序的性能。为了实现这些高增益，当将此类算法映射到硬件时，应该有效使用硅。即使这个主题是很好的研究确定性算法的情况下，没有工作已经做了随机性质的算法。该方案解决的基本问题是当随机算法映射到硬件时如何有效地利用硅片，该方案涉及基于蒙特卡罗的随机微分方程（SDEs）模拟的硬件架构的设计自动化。化学反应的随机建模和金融工程等领域是SDES广泛使用的两个例子。由于不存在或高复杂性，在推导一个解析解的一个周期，数值技术的基础上计算繁重的蒙特卡罗模拟经常被采用。基于可重构逻辑的硬件系统已经证明了上述模拟的加速和功耗降低的良好潜力。主要的技术，经常采用，并有助于实现高性能增益和显着降低功耗是使用定制的数字表示system.This项目的目的是调查有关使用现场可编程门阵列，可重构硬件设备，用于加速随机微分方程的蒙特卡罗模拟的两个关键问题。第一个问题是所采用的数字表示的质量上使用蒙特卡洛模拟的并行计算解决方案的影响，而第二个关键问题是研究和开发硬件架构和字长优化技术，目标是最小化的功耗或最大化的系统的性能，而不会显着损失的解决方案的质量。通过优化硬件系统的计算部分，执行可用资源的有效分配，从而加速整体仿真并改善每次计算操作的能耗。

Non-traditional architectures have shown massive energy savings and a significant boost on the performance of many applications across a range of domains. In order these high gains to be achieved, efficient use of silicon should be performed when such algorithms are mapped onto hardware. Even though this topic is well researched for the case of deterministic algorithms, no work has been done for algorithms of a stochastic nature. The fundamental problem that this proposal addresses is the efficiently use of silicon when a stochastic algorithm is mapped to hardware.This proposal is concerned with the design automation of hardware architectures for Monte Carlo based simulations of Stochastic Differential Equations (SDEs). Domains such as the stochastic modelling of chemical reactions and financial engineering are two examples where SDEs are widely used. Due to the non-existence or to high complexity in deriving an analytic solution for an SDE, numerical techniques based on computationally heavy Monte Carlo simulations are often employed. Hardware systems based on reconfigurable logic have demonstrated good potential for the acceleration and power consumption reduction of the above simulations. The main technique that is often employed and contributes to the realization of high performance gains and significant power consumption reduction is the use of a customized number representation system.This project aims to investigate two key issues related to the use Field Programmable Gate Arrays, a reconfigurable hardware device, for acceleration of Monte Carlo simulations for Stochastic Differential Equations. The first issue is the impact of the employed number representation on the quality of the SDE solution using Monte Carlo simulations, while the second key issue is to research and develop hardware architectures and word-length optimization techniques that target the minimization of power usage or the maximization of the performance of the system, without significant loss on the quality of the solution. By optimizing the computational part of the hardware system, efficient allocation of the available resources is performed, resulting in the acceleration of the overall simulation and improved energy consumption per computational operation.