SERT: Scale-free, Energy-aware, Resilient and Transparent Adaptation of CSE Applications to Mega-core Systems

摩尔定律和登纳德缩放导致了微处理器性能的显著提高，微处理器是现代超级计算机的基础，它由包含微处理器和存储器的节点集群组成。这种设计深深嵌入到并行编程语言、编排并行执行的运行时系统和计算科学应用程序中。多年来，这种简单、对称的设计出现了一些偏差，但现在我们已经将晶体管的规模推进到了简单让位于复杂架构的程度。登纳德尺度的缺失（已经持续了大约10年）和晶体管的原子维度对当前和未来超级计算机的架构有着深远的影响。由于数据访问局部性不足，将产生可伸缩性限制。百亿亿级系统将拥有多达100倍的核心，每个核心的内存空间和带宽也相应减少。然而，由于减少文件系统带宽而进行的原位数据分析将增加科学应用程序的内存占用。因此，我们必须改进每核数据访问的局部性，减少共享资源的争用和干扰。能源限制将从根本上限制未来大型系统的性能和可靠性。这些限制导致许多人预测会出现“暗硅”现象，即每个芯片上一半或更多的晶体管必须关闭电源才能安全运行。基于亚阈值或近阈值电压操作的低功耗处理器技术是一种可行的替代方案。然而，这些技术大大减少了大规模失败的平均时间，因此需要新的范例来维持吞吐量和正确性。不确定的性能变化将产生于设计过程的变化，这种变化会导致架构对称硬件组件的性能和功耗不对称。不对称的表现是不确定的，可以随着系统组件或软件的微小变化而变化。这种性能变化会产生不确定的、非算法的负载不平衡。可靠性限制将源于大量的系统组件，这按比例减少了平均故障时间，但也来自组件磨损和低压操作，这会引入定时误差。基础设施级别的功率封顶也可能损害应用程序的可靠性或造成严重的负载不平衡。这些技术变化的影响将像冲击波一样传遍整个软件栈。几十年来，我们基于非常严格的假设来设计计算科学应用程序，即性能是统一的，处理器是可靠的。在未来，硬件的行为将不可预测，有时是不稳定的。软件必须补偿这种行为。我们的研究预测了未来的硬件格局。我们的生态系统将结合二进制自适应、代码重构和近似计算来准备CSE应用程序。我们将为它们提供规模自由——在动态执行条件下良好运行的能力——以及至多有限的、与平台无关的代码重构。我们的软件将提供自动负载平衡和并发限制，以驯服不确定的性能变化。最后，我们的新形式的用户控制的近似计算将使CSE应用程序在低电源电压的硬件上执行，或任何形式的故障硬件，通过选择性地放弃或容忍由不可靠的执行产生的错误计算，从而节省能源。累积起来，这些工具将使主要计算科学库和应用程序（2DRMP, Code_Saturne, DL_POLY, LB3D）的非侵入式重组成为可能，并为下一代英国超级计算机做好准备。该项目与NAG合作，NAG是英国领先的高性能计算软件和服务提供商。

Moore's Law and Dennard scaling have led to dramatic performance increases in microprocessors, the basis of modern supercomputers, which consist of clusters of nodes that include microprocessors and memory. This design is deeply embedded in parallel programming languages, the runtime systems that orchestrate parallel execution, and computational science applications.Some deviations from this simple, symmetric design have occurred over the years, but now we have pushed transistor scaling to the extent that simplicity is giving way to complex architectures. The absence of Dennard scaling, which has not held for about a decade, and the atomic dimensions of transistors have profound implications on the architecture of current and future supercomputers. Scalability limitations will arise from insufficient data access locality. Exascale systems will have up to 100x more cores and commensurately less memory space and bandwidth per core. However, in-situ data analysis, motivated by decreasing file system bandwidths will increase the memory footprints of scientific applications. Thus, we must improve per-core data access locality and reduce contention and interference for shared resources.Energy constraints will fundamentally limit the performance and reliability of future large-scale systems. These constraints lead many to predict a phenomenon of "dark silicon" in which half or more of the transistors on each chip must be powered down for safe operation. Low-power processor technologies based on sub-threshold or near-threshold voltage operation are a viable alternative. However, these techniques dramatically decrease the mean time to failure at scale and, thus, require new paradigms to sustain throughput and correctness.Non-deterministic performance variation will arise from design process variation that leads to asymmetric performance and power consumption in architecturally symmetric hardware components. The manifestations of the asymmetries are non-deterministic and can vary with small changes to system components or software. This performance variation produces non-deterministic, non-algorithmic load imbalance. Reliability limitations will stem from the massive number of system components, which proportionally reduces the mean-time-to-failure, but also from the component wear and from low-voltage operation, which introduces timing errors. Infrastructure-level power capping may also compromise application reliability or create severe load imbalances.The impact of these changes on technology will travel as a shockwave throughout the software stack. For decades, we have designed computational science applications based on very strict assumptions that performance is uniform and processors are reliable. In the future, hardware will behave unpredictably, at times erratically. Software must compensate for this behavior. Our research anticipates this future hardware landscape. Our ecosystem will combine binary adaptation, code refactoring, and approximate computation to prepare CSE applications. We will provide them with scale-freedom - the ability to run well at scale under dynamic execution conditions - with at most limited, platform-agnostic code refactoring. Our software will provide automatic load balancing and concurrency throttling to tame non-deterministic performance variations. Finally, our new form of user-controlled approximate computation will enable execution of CSE applications on hardware with low supply voltages, or any form of faulty hardware, by selectively dropping or tolerating erroneous computation that arises from unreliable execution, thus saving energy. Cumulatively, these tools will enable non-intrusive reengineering of major computational science libraries and applications (2DRMP, Code_Saturne, DL_POLY, LB3D) and prepare them for the next generation of UK supercomputers. The project partners with NAG a leading UK HPC software and service provider.