Hardware Acceleration of Functional Languages (HAFLANG)

直到10年前，编程语言实现的性能还依赖于单核CPU上不断提高的时钟频率。在过去的十年里，多核时代已经兴起，在CPU中添加处理元件，以实现通用并行计算。由于CPU上的多个核心与主存之间的单一连接，具有并行支持的通用语言正在发现通用CPU架构的局限性，这些架构已经扩展了并行性。在人工智能、大数据和能源效率需求的推动下，工业正在从通用CPU转向高效的专用硬件，例如2016年谷歌的Tensorflow处理单元（TPU），华为智能手机的神经处理单元（NPU）和2017年Graphcore的智能处理单元（伊普）。这反映了一个更广泛的转移到特殊用途的硬件，以提高执行效率。函数式语言正在获得广泛使用的工业，由于减少了开发时间，更好的可维护性，代码正确性的帮助下，静态类型检查器，并容易确定性并行。函数式语言的实现主要针对通用CPU，因此对缓存行为、共享、预取和垃圾收集局部性的控制有限。因此，由于并行性和内存争用之间的权衡，它们正在达到性能极限。这个项目认为，而不是使用编译器优化挤压小增量性能改善CPU，专用硬件上的可编程FPGA可能反而能够提供一个步骤的变化，通过将这些非确定性的低效率到硬件的改进。图归约是一个功能执行模型，提供了有趣的机会，开发完全不同的处理器架构。早期的想法可以追溯到20世纪80年代，远早于过去5-10年先进的现场可编程门阵列（FPGA）技术。我们相信，为函数式语言定制的FPGA存储器层次结构可以最大限度地减少内存流量，从而避免高速缓存未命中和内存访问延迟的成本，这些成本很快成为中型和大型函数式程序的瓶颈。我们认为，降低关键运行时系统组件（预取、垃圾收集、并行性）到硬件，具有用于图缩减的域特定指令集，将大大减少运行时间。我们的目标是通过为针对特殊用途的函数式语言硬件的函数式语言开发精确的成本模型来激励计算机架构社区扩展这个项目。我们的HAFLANG项目将针对Xilinx Alveo U280加速器板，这是一种基于UltraScale+ FPGA的最先进平台，可作为开发FPU的研究工具。HAFLANG编译框架将被设计为可扩展的，因此使FPU处理器成为未来其他语言的目标。通过开发硬件加速器，我们相信有可能设计出一种处理器，（1）与在传统的中端4-16核x86/x86-64 CPU上执行的GHC编译的Haskell相比，（2）比在CPU上执行编程语言消耗的能量少四倍。

The performance of programming language implementations until 10 years ago relied on increasing clock frequencies on uni-core CPUs. The last decade has seen the rise of the multi-core era adding processing elements to CPUs, to enable general purpose parallel computing.Due to a single connection from multiple cores on a CPU to main memory, general purpose languages with parallelism support are finding the limits of general purpose CPU architectures that have been extended with parallelism. The fabric on which we compute has changed fundamentally.Driven by the needs of AI, Big Data and energy efficiency, industry is moving away from general purpose CPUs to efficient special purpose hardware e.g. Google's Tensorflow Processing Unit (TPU) in 2016, Huawei's Neural Processing Unit (NPU) in smartphones, and Graphcore's Intelligent Processing Unit (IPU) in 2017. This reflects a wider shift to special purpose hardware to improve execution efficiency.Functional languages are gaining widespread use in industry due to reduced development time, better maintainability, code correctness with assistance of static type checkers, and ease of deterministic parallelism. Functional language implementations overwhelmingly target general purpose CPUs, and hence have limited control over cache behaviour, sharing, prefetching and garbage collection locality. As such, they are reaching their performance limits due to the trade-off between parallelism and memory contention. This project takes the view that rather than using compiler optimisations to squeeze small incremental performance improvements from CPUs, special purpose hardware on programmable FPGAs may instead be able to provide a step change improvement by moving these non-deterministic inefficiencies into hardware.Graph reduction is a functional execution model that offers intriguing opportunities for developing radically different processor architectures. Early ideas stem back to the 1980s, well before the age of advanced Field Programmable Gate Array (FPGA) technology of the last 5-10 years.We believe that a bespoke FPGA memory hierarchy for functional languages could minimise memory traffic, thus avoiding the costs of cache misses and memory access latencies that quickly become the bottleneck for medium and large sized functional programs. We believe that lowering key runtime system components (prefetching, garbage collection, parallelism) to hardware, with a domain specific instruction set for graph reduction, will significantly reduce runtimes.We aim to inspire the computer architecture community to extend this project by developing accurate cost models for functional languages that target special purpose functional language hardware.Our HAFLANG project will target the Xilinx Alveo U280 accelerator board, a state-of-the-art UltraScale+ FPGA-based platform as a research vehicle for developing the FPU. The HAFLANG compilation framework will be designed to be extensible, and hence make the FPU processor a target for other languages in future.By developing a hardware accelerator, we believe it is possible to engineer a processor that (1) will execute programs with twice the throughput compared with GHC compiled Haskell executing on conventional mid-tier 4-16 core x86/x86-64 CPUs, and (2) consumes four times less energy than by executing programming languages on CPUs.