Collaborative Research: FuSe: R3AP: Retunable, Reconfigurable, Racetrack-Memory Acceleration Platform

合作研究：FuSe：R3AP：可重调、可重新配置、赛道内存加速平台

• 批准号: 2328972
• 负责人: Jingtong Hu
• 金额: $ 59.36万
• 依托单位: University of Pittsburgh
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2024
• 资助国家: 美国
• 起止时间: 2024-01-01 至 2026-12-31
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2328972&HistoricalAwards=false
• 关键词: Collaborative; Research; FuSe; R3AP; Retunable

In traditional Von Neumann computing systems, a significant bottleneck arises because the data transfer speed to and from the computing units has considerably fallen behind capacity, processing speed, and efficiency. To mitigate this bottleneck by bridging the gap between storage and computation, many innovative storage technologies have been introduced, along with near- and in-memory processing solutions designed for both emerging and traditional memory systems. Nonetheless, a considerable challenge remains: the prototyping and characterization of actual fabricated systems, especially those encompassing both mature technologies and cutting-edge technologies. To overcome this challenge, this project develops a cutting-edge Retunable and Reconfigurable Acceleration Platform (R3AP) based on emerging racetrack memory, leveraging a device-architecture-application co-design approach. The standout features of R3AP include its ability to function as a reconfigurable logic, a processing-in-memory (PIM) accelerator, and a high-density memory storage. It is retunable, meaning it can operate with bit-wise, integer, and floating-point precision, and can simulate analog-like storage and processing. R3AP effectively mitigates data movement inefficiencies while offering domain-specific acceleration and adaptability. With its dense, reliable, energy-efficient, and ultra-low latency computational capability, R3AP has the potential to revolutionize the storage and processing capabilities of future computing systems, such as those in Internet of Things (IoT) and Cyber-Physical Systems (CPS). It can also be applied to high-performance and cloud computing systems. The project's findings are shared through publications, workshops, design contests, tutorials, industrial courses, and technology transfer activities. Educational resources and outreach activity plans are made available on the project website, and software artifacts are released on GitHub.To realize R3AP, the project comprises a series of interrelated research tasks spanning multiple system layers. At the device level, the project integrates the voltage-controlled skyrmion motion mechanism with the industrial-grade 8-inch wafer magnetic tunneling junction stack and demonstrates a fully functional Skyrmion racetrack memory (SRTM), including the formation, shifting, and detection of the skyrmion stream. Additionally, it evaluates the performance of SRTM, focusing on aspects such as write-error-rate, shift-error-rate, read-error-rate, operation speed, and energy consumption. It also addresses and mitigates non-idealities, such as the pinning effect, and goes on to develop and demonstrate CMOS-integrated SRTM. On the architecture and circuit layers, the project involves the creation of a mutable lookup table, compute, and memory unit. This unit performs like multi-context Field-Programmable Gate Array (FPGA) logic, parallel PIM logic, massively parallel accumulators, and analog-like storage and compute structures, leveraging the unique properties of SRTM. This layer ensures high-speed memory access from a hierarchy consisting of banks, subarrays, tiles, etc., and further adds links via configurable switch boxes and a mesh-based network-on-chip to enable data movement operations for PIM that would otherwise be challenging. At the application layer, the project develops novel modeling, analysis, design space exploration, and runtime adjustment techniques to exploit the high degree of reconfigurability provided by R3AP. The goal is to adapt future IoT and CPS applications to changing environments and requirements, optimize resource usage, withstand external disturbances, and enhance overall system performance, resilience, and sustainability. Across all these layers, the project develops a scalable computer-aided design (CAD) flow. This involves a multi-level intermediate representation-based compilation flow, which can compile high-level description languages such as PyTorch and C/C++ into binaries for the R3AP device. This flow uses a multi-level hierarchy including front-end, middle-end, and back-end compilation of the designs, and abstracts various optimization and management problems to a suitable level for efficient resolution.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在传统的冯·诺依曼计算系统中，由于往返于计算单元的数据传输速度已经大大落后于容量、处理速度和效率，因此出现了显著的瓶颈。为了通过弥合存储和计算之间的差距来缓解这一瓶颈，人们引入了许多创新的存储技术，以及为新兴和传统存储系统设计的近内存和内存中处理解决方案。沿着。尽管如此，仍然存在相当大的挑战：实际制造系统的原型设计和表征，特别是那些包含成熟技术和尖端技术的系统。为了克服这一挑战，该项目基于新兴的赛道存储器开发了一个先进的可重新调整和可重新配置的加速平台（R3 AP），利用设备-架构-应用协同设计方法。R3 AP的突出功能包括其作为可重新配置逻辑、内存处理（PIM）加速器和高密度内存存储的能力。它是可重调的，这意味着它可以按位、整数和浮点精度操作，并且可以模拟类似于模拟的存储和处理。R3 AP有效地降低了数据移动效率，同时提供特定于域的加速和适应性。凭借其密集、可靠、节能和超低延迟的计算能力，R3 AP有可能彻底改变未来计算系统的存储和处理能力，例如物联网（IoT）和网络物理系统（CPS）。它也可以应用于高性能和云计算系统。通过出版物、讲习班、设计竞赛、教程、工业课程和技术转让活动分享该项目的成果。教育资源和推广活动计划在项目网站上提供，软件产品在GitHub上发布。为了实现R3 AP，该项目包括一系列跨越多个系统层的相互关联的研究任务。在器件层面，该项目将电压控制的Skyrmion运动机制与工业级8英寸晶圆磁性隧道结堆栈集成在一起，并展示了一个功能齐全的Skyrmion赛道存储器（SRTM），包括Skyrmion流的形成、移动和检测。此外，它评估SRTM的性能，重点是写错误率，移位错误率，读错误率，操作速度和能耗等方面。它还解决和减轻非理想性，如钉扎效应，并继续开发和演示CMOS集成SRTM。在架构和电路层，该项目涉及到创建一个可变的查找表，计算和内存单元。该单元的性能类似于多上下文现场可编程门阵列（FPGA）逻辑、并行PIM逻辑、大规模并行FPGA以及类似模拟的存储和计算结构，充分利用了SRTM的独特属性。这一层确保了从由存储体、子阵列、瓦片等组成的层次结构进行高速存储器访问，并且进一步经由可配置的开关盒和基于网格的片上网络添加链路，以实现PIM的数据移动操作，否则这将是具有挑战性的。在应用层，该项目开发了新的建模、分析、设计空间探索和运行时调整技术，以利用R3 AP提供的高度可重构性。其目标是使未来的物联网和CPS应用适应不断变化的环境和要求，优化资源使用，抵御外部干扰，并增强整体系统性能，弹性和可持续性。在所有这些层面上，该项目开发了一个可扩展的计算机辅助设计（CAD）流程。这涉及到一个基于多级中间表示的编译流程，可以将PyTorch和C/C++等高级描述语言编译成R3 AP设备的二进制文件。该流程采用多层次结构，包括前端、中间端和后端的设计编译，并将各种优化和管理问题抽象到适当的层次，以有效解决问题。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets

• DOI: 10.1109/asp-dac58780.2024.10473961
• 发表时间: 2023-11
• 期刊: 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)
• 作者: Zhuoping Yang;Shixin Ji;Xingzhen Chen;Jinming Zhuang;Weifeng Zhang;Dharmesh Jani;Peipei Zhou

SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration

• DOI: 10.1145/3626202.3637569
• 发表时间: 2024-01
• 期刊: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
• 作者: Jinming Zhuang;Zhuoping Yang;Shixin Ji;Heng Huang;Alex K. Jones;Jingtong Hu;Yiyu Shi;Peipei Zhou

AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP

目的：在异构可重构计算平台 Versal ACAP 上加速任意精度整数乘法

• DOI: 10.1109/iccad57390.2023.10323754
• 发表时间: 2023
• 期刊: IEEE
• 作者: Yang, Zhuoping;Zhuang, Jinming;Yin, Jiaqi;Yu, Cunxi;Jones, Alex K.;Zhou, Peipei
• 通讯作者: Zhou, Peipei