III-V quantum dot lasers grown on patterned silicon and SOI substrates by MBET first year

在硅平台上集成III-V材料和器件是高效光子光源和高移动性电子器件的强劲需求。然而，直接外延生长存在重大挑战，包括反相边界（apb），螺纹位错（td）和微裂纹。近年来，在利用几微米的III-V缓冲层减少这三种缺陷方面取得了重大进展。此外，III-V层的总厚度被限制在几微米（< 6um），这是由于III-V层与Si衬底之间热膨胀不匹配而形成的微裂纹造成的。在这个项目中，我们将利用图案化硅的潜力来抑制Si或SOI衬底上图案化区域内的缺陷形成。最重要的是，我们希望利用UCL的双mbe系统，通过生长Si和Ge等iv族材料，在图案区域内生长纳米尺寸的孔洞，以放松III-V层与硅衬底之间的应变，从而解决III-V层与硅衬底之间热膨胀不匹配的问题。

There is a strong demand for integrating of III-V materials and devices on silicon platform for high-efficient photonics light sources and high mobility electronics devices. However, there are significant challenges for direct epitaxial growth, including anti-phase boundaries (APBs), threading dislocations (TDs) and micro-cracks. In last few years, significant progress has been made in reducing these three types of defects with a few micrometre III-V buffer layers. In addition, the total thickness of III-V layers is limited to a few micrometres (< 6um) by the formation of micro-cracks due to a mismatch in thermal expansion between the III-V epilayers and a Si substrate. In this project, we will exploit the potential of patterned silicon to suppress the defect formation within the patterned area on Si or SOI substrates. Most importantly, we would like to grow nano-size holes within the patterned areas by grow group-IV materials, such as Si and Ge by using twin-MBE system at UCL to relax the strain between III-V layers and silicon substrates, and hence to solve the problem due to thermal expansion mismatch between III-V layers and silicon substrates.