Efficient Application Mapping for Massively Parallel Systems

大规模并行计算架构（如GPU和FPGA）正变得越来越流行，因为与传统的高性能计算方法相比，它们提供了更大的并行能力和更多的特定于应用的处理能力。基于图的问题特别适合于大规模并行：大量的小处理元素执行简单的计算，使用小消息相互交互。尽管基于图的大规模并行问题无处不在，但如何将这些问题映射到硬件上仍然是一个未探索的问题，部分原因是硬件直到最近才能够支持真正的大规模并行。这是一个重大的研究机会，在开发高效的，通用的映射算法的并行系统，可以从一个抽象的图形表示的问题，并产生一个硬件图形表示的问题映射到物理硬件。

Massive parallel compute architectures such as GPUs and FPGAs are becoming increasingly popular, as they offer greater parallelism capabilities and more application-specific processing capability, compared to traditional high-performance computing approaches. Graph-based problems are particularly amenable to massive parallelism: a large number of small processing elements performing simple computation, that interact with each other using small messages.Despite the ubiquity of graph-based massive parallel problems, determining how to map such problems onto hardware remains a largely unexplored problem, in part because hardware has only recently become available able to support the truly massive parallelism. This is a major research opportunity in the development of efficient, general-purpose mapping algorithms for parallel systems that can start from an abstract graph representation of the problem and produce a hardware graph representing the problem as mapped to the physical hardware.