Low-Power Programmable Switch Architecture

如何通过低功耗设计降低数字集成电路的功耗已成为后摩尔时代的重要课题之一。这个问题在可编程开关领域尤为重要。由于部署的交换机数量巨大，单个交换机的功耗略微增加将导致整个网络的总功耗显著增加，反之亦然。因此，通过低功耗设计降低总功耗的效果是可观的，对减少碳排放的贡献也是不言而喻的。协议独立交换架构（比萨）是研究界使用的主流可编程交换架构。它在匹配字段和分组处理操作方面具有优势，并且具有更高的软件定义网络操作灵活性。然而，比萨架构由于其工作原理，在功耗性能方面存在固有缺陷，无法直接启用低功耗设计技术。此外，大多数基于架构的研究都集中在提高性能或功能上。很少有研究在功耗性能和与低功耗设计技术的兼容性方面取得重大进展。因此，为了实现低功耗设计技术，降低功耗，一种新的可编程开关架构的建议可以被视为一个可行的和有前途的解决方案，本研究的重点是设计一种新的可编程开关架构，可以降低可编程开关的功耗，同时保持类似或更好的性能相比，目前的主流架构比萨。具体来说，可以分为三个部分：1.设计一种新的可编程交换机架构，能够实现低功耗设计技术，避免比萨在功耗方面的缺点.研究新架构下先进的低功耗设计技术动态频率和电压调节（DVFS）.为新架构开发编译器和开发工具在比萨架构中，用于处理包的流水线仅在软件级别被划分为多个阶段。然而，这可能导致硬件资源和功耗的浪费。因此，我们可以通过设计一个新的架构，在硬件层面上将这些阶段分开，在形成流水线时只使用所需的阶段。这种设计还允许新架构使用低功耗设计技术来降低功耗。例如，使用时钟门控和功率门控来完全关闭未使用的级。DVFS是最强大的低功耗设计技术之一。它可以随着业务量的变化而改变开关的工作频率和电压，以达到最小的功耗。然而，交通的变化无法预测。如果DVFS只以流量作为指标，开关频率和电压的频繁变化会造成更多的功耗浪费。因此，目前还没有DVFS在可编程开关中的应用研究。本研究将通过改进新的架构，在可编程交换机中实现DVFS。并通过控制平面在宏观层面上监控流量，以及约束流量切换策略，来预测流量，从而降低功耗，提高交换机的能效。此外，为了便于将来的研究和社区使用新架构，有必要为新架构设计一个编译器和相应的开发工具（软件包、软件框架、可视化编程）。所有这些工具都将是开源的，可以降低开发新架构的学习成本，并使新架构得到更广泛的应用。该项目属于EPSRC ICT网络和分布式系统研究领域。福尔斯。

Now, how to reduce the power consumption of digital integrate circuit through low-power design has become one of the most important problems in the post-Moore era. This problem is particularly important in the field of programmable switch. Due to the enormous number of switches deployed, a slight increase in the power consumption of a single switch will lead to a significant increase in the total power consumption of the whole network and vice versa. Therefore, the effect of reducing total power consumption through low-power design is substantial, and the contribution to reducing carbon emissions is self-evident.Protocol Independent Switching Architecture (PISA) is the mainstream programmable switch architecture used in the research community. It has superiority in matching fields and packet processing operations, as well as higher flexibility of Software Defined Network operations. However, PISA architecture has inherent defects in power consumption performance due to its working principle and cannot enable low power design technologies directly. In addition, most architecture-based research focuses on improving performance or function. Few research has made significant advances in power consumption performance and compatibility with low-power design technologies. Therefore, to enable low-power design technologies and reduce power consumption, the proposal of a new programmable switch architecture can be regarded as a feasible and promising solution.This research focuses on designing a novel programmable switch architecture that can reduce the power consumption of programmable switches while maintaining similar or better performance compared to the current mainstream architecture PISA. Specifically, it can be divided into three parts:1. Design a new programmable switch architecture that can enable low-power design technologies and avoid the drawbacks of PISA in terms of power consumption.2. Investigate the advanced low power design technology Dynamic Frequency and Voltage Scaling (DVFS) on new architecture.3. Develop the compiler and development tools for new architectureIn the PISA architecture, the pipeline used to process packages is divided into multiple stages only at the software level. However, this can lead to waste of hardware resources and power consumption. Therefore, we can separate these stages at the hardware level by designing a new architecture, and only use the required stages when forming the pipeline. This design also allows the new architecture to use low-power design technologies to reduce the power consumption. For example, using clock gating and power gating to completely shut down the unused stages.DVFS is one of the most powerful low-power design technologies. It can change the operating frequency and voltage of the switch with changes in traffic to achieve the minimum power consumption. However, changes in traffic cannot be predicted. If DVFS only uses traffic as an indicator, frequent changes in frequency and voltage of the switch will result in more waste of power consumption. Therefore, there is currently no research focuses on the application of DVFS in programmable switches. This research will implement DVFS in programmable switches by improving the new architecture. And predict traffic by monitoring traffic at the macro level through control planes, as well as constraining traffic switching strategies, to reduce power consumption and increase power efficiency of the switch.Besides, to facilitate the use of new architecture for future research and community, it is necessary to design a compiler and corresponding development tools (Software package, software framework, visual programming) for new architecture. All these tools will be open source, which can reduce the learning cost for the development of new architecture and make the new architecture more widely used.This project falls within the EPSRC ICT networks and distributed systems research area.