Advanced Design, Partitioning and Test for System-in-Package Electronics

ADEPT-SiP项目旨在为新型系统级封装电子产品功能开发和演示一种严格的、首次正确的设计和供应链管理方法。该项目将解决原理图捕获，分区和有源器件，基板和封装设计，以满足特定的性能，成本，尺寸和重量目标。其他关键设计阶段将包括热设计和EMC设计，以及针对制造、测试、可靠性和环境影响的设计。将设计和模拟新型高密度嵌入式无源衬底技术，进行工艺表征，并为全系列无源元件和互连和组装结构开发参数化元件模型。核心设计、模拟和建模活动将在系统级封装技术演示中得到验证。

The ADEPT-SiP project is directed at the development and demonstration of a rigorous, right-first-time design and supply chain management methodology for novel System-in-Package Electronics Product Functions. The project will address schematic capture, partitioning and active device, substrate and package design to meet specific performance, cost, size and weight targets. Other key design stages will include thermal and EMC design, and design-for-manufacture, test, reliability and for environmental impact. Novel, high density embedded passive substrate technologies will be designed and simulated, process characterisation undertaken and parameterised component models developed for the full range of passive components and interconnection and assembly structures. The core design, simulation and modelling activities will be proven in System-in-Package technology demonstrators.