Integrated Optics for High Performance and Energy Efficient Processors

今天，从数据中心到边缘计算设备，大多数硬件计算系统的设计都是由高速处理大量数据的需求驱动的。需要向以数据为中心的架构转变，以实现自动驾驶汽车、去中心化网络、认知网络物理系统、6G等众多应用的部署。这自然需要集成光学技术来实现快速的芯片级通信和数据处理。随着硅光子学的成熟和复杂器件的实现，新的计算机组织现在需要在大规模集成电路中充分利用该技术。这导致了拟议的研究计划，旨在弥合设备设计人员和计算机架构开发人员之间的差距。该项目的长期目标是基于硅光子学技术的颠覆性硬件架构的设计。目标是提高集成计算系统的吞吐量、延迟和能源效率。为此，申请人打算利用硅光子学的最新进展来设计能够在传输过程中处理数据的架构。紧凑和超快的光加速器将被设计并嵌入到一个非易失性可重构的片上光互连中。该网络将由一个能够预校准光学设备的智能网络接口配置，该接口将使用可扩展和精确的仿真框架进行评估。研究目标（RO）总结如下：RO1，短期：设计和模拟基于硅光子学的架构的框架。该框架将利用现场可编程门阵列（FPGA）加速，对基于硅光子学的架构进行可扩展和准确的评估。RO2，短期：智能光网络接口。为了减少通信延迟，将开发一种能够根据芯片实时活动预测通信的网络接口。该接口将涉及嵌入式学习技术来校准光学设备。中期RO3：走向颠覆性的计算机架构。目标是将硅光子学置于计算架构的中心阶段，以便充分利用该技术进行高速处理和数据传输。光硬件加速器将集成在互连中，以减少光电（EO/OE）转换器的数量。开发光学元件和电路的加拿大公司将直接受益于该计划的跨学科性质，以设计用于数据密集型应用的光学加速器。开发嵌入式计算系统的公司可以使用开发的解决方案来提高硬件架构的性能。

Context Today, the design of most hardware computing systems, from data centers to edge computing devices, is driven by the need to process massive amounts of data at high rate. The shift to data-centric architectures is needed to allow for the deployment of numerous applications such as autonomous vehicles, decentralized web, cognitive cyber-physical systems, 6G and beyond. This naturally calls for integrated optics technology for fast chip-scale communication and data processing. As silicon photonics is maturing and enables the realization of ever complex devices, new computer organizations are now required to fully take advantage of the technology in very large scale integrated circuits. This leads to the proposed research program which aims at bridging the gap between device designers and computer architecture developers. Objectives The long-term objective of the program is the design of disruptive hardware architectures based on silicon photonics technology. The goal is to improve throughput, latency and energy efficiency of integrated computing systems. To this end, the applicant intends to take advantages of the latest advances in silicon photonics to design architectures capable of processing data during their transmission. Compact and ultra-fast optical accelerators will be designed and embedded in a non-volatile reconfigurable on-chip optical interconnect. The network will be configured by a smart network interface able to pre-calibrate optical devices, which will be evaluated using a scalable and accurate emulation framework. The Research Objectives (RO) are summarized as follow: RO1, short-term: framework to design and emulate silicon photonics-based architectures. The framework will take advantage of Field Programmable Gate Array (FPGA) acceleration for scalable and accurate evaluation of the silicon photonics-based architectures. RO2, short-term: smart optical network interface. In order to reduce communication latency, a network interface capable of anticipating communication according to real-time chip activity will be developed. The interface will involve embedded learning techniques to calibrate the optical devices. RO3, mid-term: toward disruptive computer architectures. The goal is to place silicon photonics at center stage of computing architectures in order to make full use of the technology for high speed processing and data transfer. Optical hardware accelerators will be integrated in the interconnects to reduce the number of Electro-Optic and Opto-Electronic (EO/OE) converters. Impact Canadian companies developing optical components and circuits will be benefitted directly from the cross-disciplinary nature of the program to design optical accelerators for data intensive applications. Companies developing embedded computing systems may use the developed solutions to increase the performance of hardware architectures.