IR-ATA: IR Annotated Timing Analysis, A Flow for Closing the Loop Between PDN Design, IR Analysis & Timing Closure
IR-ATA: IR Annotated Timing Analysis, A Flow for Closing the Loop Between PDN Design, IR Analysis & Timing Closure
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IR-ATA：IR 注释时序分析、用于闭合 PDN 设计、IR 分析之间循环的流程
DOI：
10.1145/3287624.3287683
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发表时间：
2019
期刊：
影响因子：
--
通讯作者：
Avesta Sasan
中科院分区：
文献类型：
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作者：
Ashka Vakil;H. Homayoun;Avesta Sasan
本文介绍了IR-ATA，这是一种新颖的流动，用于建模IR滴剂在ASIC芯片的物理设计和时机闭合期间的时机影响。我们首先说明当前和常规的预算预算IR下降和电压噪声（通过使用硬边缘）如何导致次优设计。因此，我们提出了一种针对电压噪声进行建模和边缘的新方法，以便根据其自身拓扑和自身对电压噪声的看法将每个正时路径划分。通过具有这样的基于路径的边缘机制，设计中大多数定时路径的IR滴和电压噪声的边缘可以安全放松。边距的减小增加了可用的时正松弛时间，可用于改善设计的功率，性能和区域。最后，我们说明了如何使用IR-ATA来跟踪物理或PDN变化的时间影响，从而使物理设计人员能够探索以前由于缺乏方法论而无法实现的权衡。
This paper presents IR-ATA, a novel flow for modeling the timing impact of IR drop during the physical design and timing closure of an ASIC chip. We first illustrate how the current and conventional mechanism for budgeting the IR drop and voltage noise (by using hard margins) lead to sub-optimal design. Consequently, we propose a new approach for modeling and margining against voltage noise, such that each timing path is margined based on its own topology and its own view of voltage noise. By having such a path based margining mechanism, the margins for IR drop and voltage noise for most timing paths in the design are safely relaxed. The reduction in the margin increases the available timing slack that could be used for improving the power, performance, and area of a design. Finally, we illustrate how IR-ATA could be used to track the timing impact of physical or PDN changes, allowing the physical designers to explore tradeoffs that were previously, for lack of methodology, not possible.
对 SAT 求解器在击败混淆方案方面的能力和局限性进行基准测试
DOI：
10.1109/iolts.2018.8474189
发表时间：
2018
期刊：
2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS
影响因子：
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作者：
Roshanisefat, Shervin;Thirumala, Harshith K.;Gaj, Kris;Homayoun, Houman;Sasan, Avesta
通讯作者：
Sasan, Avesta
SRCLock：用于保护硬件的抗 SAT 循环逻辑锁定
DOI：
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发表时间：
2018
期刊：
Proceedings of the 2018 on Great Lakes Symposium on VLSI
影响因子：
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作者：
Roshanisefat, Shervin;Mardani Kmali, Hadi;Sasan, Avesta
通讯作者：
Sasan, Avesta
LUT-Lock：一种新颖的基于 LUT 的逻辑混淆，用于 FPGA 比特流和 ASIC 硬件保护
DOI：
10.1109/isvlsi.2018.00080
发表时间：
2018
期刊：
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI
影响因子：
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作者：
Mardani Kamali, Hadi;Zamiri Azar, Kimia;Gaj, Kris;Homayoun, Houman;Sasan, Avesta
通讯作者：
Sasan, Avesta