FPGA-Based Processor Acceleration for Image Processing Applications.

FPGA-Based Processor Acceleration for Image Processing Applications.
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DOI:
10.3390/jimaging5010016
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发表时间:
2019-01-13
期刊:
影响因子:
3.2
通讯作者:
Crookes D
Crookes D
中科院分区:
其他
文献类型:
--
作者:
Siddiqui F;Amiri S;Minhas UI;Deng T;Woods R;Rafferty K;Crookes D

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基于 FPGA 的嵌入式图像处理系统提供了大量的计算资源,但与软件系统相比,存在编程挑战。该论文描述了一种基于 FPGA 软处理器(称为图像处理处理器 (IPPro))的方法,该处理器可在高端 Xilinx FPGA 系列上运行高达 337 MHz,并详细介绍了基于数据流的编程环境。该方法针对 k-means 聚类操作和交通标志识别应用进行了演示,这两种应用均已在具有 Xilinx Zynq-7000 片上系统 (SoC) 的 Avnet Zedboard 上进行了原型设计。探索了许多并行数据流映射选项,与基于 ARM 的同等软件实现相比,使用 16 个 IPPro 内核的 k 均值聚类速度提高了 8 倍,使用 16 个 IPPro 内核的交通标志识别的形态过滤操作速度提高了 9.6 倍。我们表明,对于 k 均值聚类,16 个 IPPro 内核实现的能效 (fps/W) 分别比 ARM Cortex-A7 CPU、nVIDIA GeForce GTX980 GPU 和 ARM Mali-T628 嵌入式 GPU 高 57 倍、28 倍和 1.7 倍。
FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively.
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