CONCEALING-Gate: Optical Contactless Probing Resilient Design
CONCEALING-Gate: Optical Contactless Probing Resilient Design
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CONCEALING-Gate：光学非接触式探测弹性设计
DOI：
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发表时间：
2021
影响因子：
2.2
通讯作者：
Navid Asadizanjani
中科院分区：
文献类型：
--
作者：
M. T. Rahman;Nusrat Farzana;Dhwani Mehta;Shahin Tajik;M. Tehranipoor;Navid Asadizanjani
光学探测虽然是作为芯片背面的硅调试工具开发的，但已经显示出其从现代片上系统设备中提取秘密数据（如密钥和用户身份）的能力。现有的光学探测对策是基于在资产提取期间检测任何设备修改尝试或操作条件的突然变化。这些对策通常需要额外的制造步骤，并导致面积和功率开销。在这篇文章中，我们提出了一种新的低开销设计方法，以防止光探测。它利用被称为“隐蔽门”的附加操作逻辑门，作为连接到承载资产信号的网络的逻辑门的相邻门插入。资产携带逻辑的切换活动与隐藏门的切换活动重叠。输入信号和隐藏门的布局必须以这样的方式选择，即它们在防止光学探测的不同变体方面保持同样有效，即，电光频率测绘和电光探测。该方法适用于现有的ASIC/FPGA设计流程和制造过程，因为不需要设计新的标准逻辑单元。我们已经进行了全面的安全评估的隐藏门使用的安全度量的基础上开发的参数是至关重要的光学探测。攻击弹性的逻辑单元，保护隐藏门，使用基于实证研究的仿真方法和实验验证进行评估。我们的分析表明，在隐藏门的存在下，逻辑单元实现高弹性对光学非接触式探测技术。
Optical probing, though developed as silicon debugging tools from the chip backside, has shown its capability of extracting secret data, such as cryptographic keys and user identifications, from modern system-on-chip devices. Existing optical probing countermeasures are based on detecting any device modification attempt or abrupt change in operating conditions during asset extraction. These countermeasures usually require additional fabrication steps and cause area and power overheads. In this article, we propose a novel low-overhead design methodology to prevent optical probing. It leverages additional operational logic gates, termed as “CONCEALING-Gates,” inserted as neighbor gates of the logic gates connected to the nets carrying asset signals. The switching activity of the asset carrying logic is camouflaged with the switching activity of the concealing-gate. The input signal and placement in the layout of the concealing-gates must be selected in such a way that they remain equally effective in preventing different variants of optical probing, i.e., electro-optical frequency mapping and Electro-optical probing. The methodology is suitable for the existing ASIC/FPGA design flow and fabrication process, since designing new standard logic cells is not required. We have performed a comprehensive security evaluation of the concealing-gates using a security metric developed based on the parameters that are crucial for optical probing. The attack resiliency of the logic cells, protected by concealing-gates, is evaluated using an empirical study-based simulation methodology and experimental validation. Our analysis has shown that in the presence of concealing-gates, logic cells achieve high resiliency against optical contactless probing techniques.
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DOI：
10.13154/tches.v2019.i3.86-118
发表时间：
2019-05
期刊：
IACR Trans. Cryptogr. Hardw. Embed. Syst.
影响因子：
--
作者：
Bicky Shakya;Haoting Shen;M. Tehranipoor;Domenic Forte
通讯作者：
Bicky Shakya;Haoting Shen;M. Tehranipoor;Domenic Forte
DOI：
--
发表时间：
2019
期刊：
IEEE Asian Hardware Oriented Security and Trust Symposium
影响因子：
--
作者：
Covic, Ana;Shi, Qihang;Shen, Haoting;Forte, Domenic
通讯作者：
Forte, Domenic
论光学攻击使逻辑混淆变得脆弱
DOI：
--
发表时间：
2020
期刊：
ITC-asia
影响因子：
--
作者：
Leonidas Lavdas, M Tanjidur
通讯作者：
Leonidas Lavdas, M Tanjidur
DOI：
10.1109/ivsw.2018.8494856
发表时间：
2018
期刊：
2018 IEEE 3rd International Verification and Security Workshop (IVSW
影响因子：
--
作者：
Rahman, M Tanjidur;Shi, Qihang;Tajik, Shahin;Shen, Haoting;Woodard, Damon L.;Tehranipoor, Mark;Asadizanjani, Navid
通讯作者：
Asadizanjani, Navid