Accelerating Large Garbled Circuits on an FPGA-enabled Cloud
Accelerating Large Garbled Circuits on an FPGA-enabled Cloud
复制标题
在支持 FPGA 的云上加速大型乱码电路
DOI:
10.1109/h2rc49586.2019.00008
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发表时间:
2019
期刊:
影响因子:
--
通讯作者:
Ioannidis, Stratis
中科院分区:
文献类型:
--
作者:
Leeser, Miriam;Gungor, Mehmet;Huang, Kai;Ioannidis, Stratis
Garbled Circuits (GC) is a technique for ensuring the privacy of inputs from users and is particularly well suited for FPGA implementations in the cloud where data analytics is frequently run. Secure Function Evaluation, such as that enabled by GC, is orders of magnitude slower than processing in the clear. We present our best implementation of GC on Amazon Web Services (AWS) that implements garbling on Amazon's FPGA enabled F1 instances. In this paper we present the largest problems garbled to date on FPGA instances, which includes problems that are represented by over four million gates. Our implementation speeds up garbling 20 times over software over a range of different circuit sizes.
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2017 IEEE International Conference on Computer Design (ICCD)
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影响因子:
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通讯作者:
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