Garbled Circuits in the Cloud using FPGA Enabled Nodes

Garbled Circuits in the Cloud using FPGA Enabled Nodes
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使用支持 FPGA 的节点的云中的乱码电路

DOI:
10.1109/hpec.2019.8916407
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发表时间:
2019
期刊:
2019 IEEE High Performance Extreme Computing Conference (HPEC
影响因子:
--
通讯作者:
Leeser, Miriam
Leeser, Miriam
中科院分区:
--
文献类型:
--
作者:
Huang, Kai;Gungor, Mehmet;Fang, Xin;Ioannidis, Stratis;Leeser, Miriam

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数据隐私在我们相互关联的世界中越来越受到关注。乱码电路是安全功能评估(SFE)的一种重要方法,但其存在乱码时间长的问题。在本文中,我们使用Amazon Web Services,特别是Amazon F1 FPGA启用的节点,在云中呈现乱码电路。我们在软件中实现了混淆器和评估器,并展示了F1实例如何加速混淆过程并快速适应几个不同的应用程序。在AWS上测量的实验结果表明,使用FPGA进行的混淆加速了15倍。这将导致总的应用程序加速,包括乱码,通信和评估,在大范围的应用程序大小接近三倍。
Data privacy is an increasing concern in our interconnected world. Garbled circuits is an important approach used for Secure Function Evaluation (SFE); however it suffers from long garbling times. In this paper we present garbled circuits in the cloud using Amazon Web Services, and particularly Amazon F1 FPGA enabled nodes. We implement both garbler and evaluator in software, and show how F1 instances can accelerate the garbling process and rapidly adapt to several different applications. Experimental results, measured on AWS, indicate a 15 times speedup for garbling done using an FPGA. This results in total application speedup, including garbling, communications and evaluation, of close to three times over a large range of application sizes.
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