Modeling and Analysis of a Frequency-Locked Loop Based on Two-Stage Ring Voltage-Controlled Oscillator
Modeling and Analysis of a Frequency-Locked Loop Based on Two-Stage Ring Voltage-Controlled Oscillator
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基于两级环形压控振荡器的锁频环建模与分析
DOI：
10.1007/s00034-021-01694-w
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发表时间：
2021-04
期刊：
影响因子：
--
通讯作者：
Sun Weifeng
中科院分区：
文献类型：
--
作者：
Wu Jin;Sun Xingsheng;Zhou Mouzhao;Rong Yue;Zheng Lixia;Sun Weifeng
In this paper, an analytical model of a closed-loop frequency-locked loop (FLL) based on a two-stage voltage-controlled oscillator (VCO) is proposed. Switch capacitor technology is used to accelerate the conversion speed of the frequency-to-voltage converter for reducing the locking time. The VCO is reduced to the minimum two-stage delay ring structure for outputting high-frequency signals with less variation caused by process, voltage, and temperature drift. Based on the strategy that focuses on the optimization of the loop bandwidth, a low jitter GHz clock with a wide swing and a strong capacitive load driving ability is realized. The proposed FLL is implemented in TSMC 0.35 μm 3.3 V CMOS process. From the experimental results, the output frequency is ranged from 750 MHz to 1.27 GHz, and the RMS jitter of the output clock is less than 36 ps under 1.039 GHz. The generated low-jitter clock is suitable for GHz gating applications in single-photon detection.
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DOI：
10.1109/tcsii.2013.2251938
发表时间：
2013-03
期刊：
IEEE Transactions on Circuits and Systems II: Express Briefs
影响因子：
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作者：
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通讯作者：
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DOI：
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发表时间：
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期刊：
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影响因子：
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DOI：
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发表时间：
2009-11
期刊：
2009 Proceedings of ESSCIRC
影响因子：
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DOI：
10.1109/isscc.2017.7870276
发表时间：
2017-02
期刊：
2017 IEEE International Solid-State Circuits Conference (ISSCC)
影响因子：
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Karthik Pappu;G. Reitsma;S. Bapat
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影响因子：
3.8
作者：
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通讯作者：
Peng Cheng-Zhi