Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders

Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders
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减少随机 LDPC 解码器中解码周期的策略

DOI:
10.1109/tcsii.2016.2535038
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发表时间:
2016-02
期刊:
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS
影响因子:
--
通讯作者:
Xiaoyang Zeng
Xiaoyang Zeng
中科院分区:
其他
文献类型:
--
作者:
Di Wu;Yun Chen;Qichen Zhang;Yeong-luh Ueng;Xiaoyang Zeng

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提出了基于查找表的初始化、基于比特翻转的后处理和基于后验信息的硬判决三种策略,以减少随机低密度奇偶校验译码的译码周期数。对于标准IEEE 802.3an码,仿真表明,在令人满意的比特错误率的DC的平均数量减少了73.6%。此外,硬件实现表明,所提出的解码器所需的面积显着减少。
This brief presents three strategies, including initialization based on Look Up Table (LUT), postprocessing based on bit flipping and hard decision based on the posterior information, to reduce the number of decoding cycles (DCs) for stochastic low-density parity-check decoding. For the standard IEEE 802.3an code, simulation indicates a 73.6% reduction in the average number of DCs with a satisfactory bit error rate. Moreover, hardware implementation shows that the area required for the proposed decoder is significantly reduced.
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