Strong Anti-SAT: Secure and Effective Logic Locking
Strong Anti-SAT: Secure and Effective Logic Locking
复制标题
强抗SAT：安全有效的逻辑锁定
DOI：
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复制
发表时间：
2020
期刊：
影响因子：
--
通讯作者：
Ankur Srivastava
中科院分区：
文献类型：
--
作者：
Yuntao Liu;Michael Zuzak;Yang Xie;Abhishek Chakraborty;Ankur Srivastava
逻辑锁定被认为是针对IC供应链中的安全威胁的知识产权(IP)的强有力的保护，特别是当制造设施不可信的时候。当密钥不正确时，这种技术使用额外的锁定电路来向数字功能注入不正确的行为。一系列被称为“SAT攻击”的攻击提供了一个强大的数学公式来找到锁定电路的正确密钥。当密钥不正确时，许多传统的SAT弹性逻辑锁定方案无法向电路注入足够的错误：通常有很少(或只有一个)在电路输出[18]、[20]-[22]处引起任何错误的输入项。最先进的剥离功能逻辑锁定(SFLL)[24]技术提供了广泛的配置，在安全性(即SAT攻击的复杂性)和有效性(即错误密钥注入的错误量)之间引入了权衡。在这项工作中，我们证明了这种权衡在所有逻辑锁定技术中是通用的。为了在不牺牲安全性的前提下获得高效的锁定效果，我们提出了一种新的安全有效的逻辑锁定方案，称为强反SAT(强抗SAT)方案。与现有技术相比，SAS有以下重大改进。(1)我们证明了SAS抵抗SAT攻击的安全性不会因为有效性的提高而受到影响。(2)与以往只关注电路级锁定影响的工作不同，我们将SA锁定的模块集成到80386处理器中，并表明SAS具有高应用程序级影响。(3)SAS的硬件开销小于现有技术。
Logic locking has been proposed as strong protection of intellectual property (IP) against security threats in the IC supply chain especially when the fabrication facility is untrusted. Such techniques use additional locking circuitry to inject incorrect behavior into the digital functionality when the key is incorrect. A family of attacks known as “SAT attacks” provides a strong mathematical formulation to find the correct key of locked circuits. Many conventional SAT-resilient logic locking schemes fail to inject sufficient error into the circuit when the key is incorrect: there are usually very few (or only one) input minterms that cause any error at the circuit output [18], [20]–[22]. The state-of-the-art stripped functionality logic locking (SFLL) [24] technique provides a wide spectrum of configurations which introduced a trade-off between security (i.e. SAT attack complexity) and effectiveness (i.e. the amount of error injected by a wrong key). In this work, we prove that such a trade-off is universal among all logic locking techniques. In order to attain high effectiveness of locking without compromising security, we propose a novel secure and effective logic locking scheme, called Strong Anti-SAT (SAS). SAS has the following significant improvements over existing techniques. (1) We prove that SAS's security against SAT attack is not compromised by increases in effectiveness. (2) In contrast to prior work which focused solely on the circuit-level locking impact, we integrate SAS-locked modules into an 80386 processor and show that SAS has a high application-level impact. (3) SAS's hardware overhead is smaller than that of existing techniques.
Full-Lock：使用完全可配置逻辑和路由块进行混淆电路的 SAT 实例的硬分配
DOI：
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发表时间：
2019
期刊：
DAC 2019
影响因子：
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作者：
Kamali, Hadi Mardani;Zamiri Azar, Kimia;Homayoun, Houman;Sasan, Avesta
通讯作者：
Sasan, Avesta
DOI：
10.1145/3060403.3060469
发表时间：
2017-05
期刊：
Proceedings of the Great Lakes Symposium on VLSI 2017
影响因子：
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作者：
Yuanqi Shen;H. Zhou
通讯作者：
Yuanqi Shen;H. Zhou
DOI：
10.1109/tcad.2019.2944586
发表时间：
2020-10-01
影响因子：
2.9
作者：
Chakraborty, Abhishek;Jayasankaran, Nithyashankari Gummidipoondi;Zuzak, Michael
通讯作者：
Zuzak, Michael