STFL: Energy-Efficient Data Movement with Slow Transition Fast Level Signaling

STFL: Energy-Efficient Data Movement with Slow Transition Fast Level Signaling
复制标题

STFL:具有慢速转换快速电平信号传输的节能数据移动

DOI:
10.1145/3316781.3317819
复制
发表时间:
2019
期刊:
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019
影响因子:
--
通讯作者:
Bojnordi, Mahdi N.
Bojnordi, Mahdi N.
中科院分区:
--
文献类型:
--
作者:
Behnam, Payman;Bojnordi, Mahdi N.

文献摘要

参考文献

被引文献

相似文献

在现代计算机系统中,大型高速缓存中的数据移动消耗大量的能量。已经提出了低功率接口来解决这个问题。不幸的是,这些技术的能量效率在很大程度上受到限制,这是由于低功率线的不适当的延迟开销和复杂的编码机制。本文提出了一种混合技术慢过渡,快级(STFL)信令,创建一个平衡的最后一级缓存接口的功率和带宽。结合STFL码,信令技术显著减轻了低功率线的性能影响,从而提高了存储器系统中数据移动的能量效率。当应用于当代多核系统的最后一级缓存时,STFL与电压频率缩放基线相比将CPU能量延迟产品提高了9%。此外,所提出的架构减少了26%的CPU能量,并实现了98%的高性能基线所提供的性能。
Data movement in large caches consumes a significant amount of energy in modern computer systems. Low power interfaces have been proposed to address this problem. Unfortunately, the energy-efficiency of these techniques is largely limited due to undue latency overheads of low power wires and complex coding mechanisms. This paper proposes a hybrid technique for slow-transition, fast-level (STFL) signaling that creates a balance between power and bandwidth in the last level cache interface. Combined with STFL codes, the signaling technique significantly mitigates the performance impacts of low power wires, thereby improving the energy efficiency of data movement in memory systems. When applied to the last level cache of a contemporary multicore system, STFL improves the CPU energy-delay product by 9% as compared to a voltage-frequency scaled baseline. Moreover, the proposed architecture reduces the CPU energy by 26% and achieves 98% of the performance provided by a high-performance baseline.
能量延迟积
DOI: --
发表时间: 2013
期刊:
影响因子: --
作者:
J. Laros;K. Pedretti;S. M. Kelly;W. Shu;Kurt B. Ferreira;J. Vandyke;C. Vaughan
通讯作者: C. Vaughan
利用数据值相似性的 DRAM 通道中的节能数据编码
DOI: --
发表时间: 2016
期刊: International Symposium on Computer Architecture
影响因子: --
作者:
Hoseok Seol;Wongyu Shin;Jaemin Jang;Jungwhan Choi;Jinwoong Suh;L. Kim
通讯作者: L. Kim
用于高性能互连的转换编码动态总线技术
DOI: --
发表时间: 2002
期刊: 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)
影响因子: --
作者:
M. Anders;N. Rai;R. Krishnamurthy;S. Borkar
通讯作者: S. Borkar
用于 NM 技术中动态电压缩放的互连感知延迟模型
DOI: --
发表时间: 2009
期刊: ACM Great Lakes Symposium on VLSI
影响因子: --
作者:
H. Zarrabi;A. Al;Y. Savaria
通讯作者: Y. Savaria
用于节能大型缓存架构的自适应基于时间的编码
DOI: --
发表时间: 2017
期刊: E2SC@SC
影响因子: --
作者:
Payman Behnam;N. Sedaghati;M. N. Bojnordi
通讯作者: M. N. Bojnordi