State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
复制标题
基于 MLC STT-RAM 的寄存器的状态转换感知溢出启发式
DOI：
10.1155/2017/1030249
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发表时间：
2017-11
期刊：
影响因子：
--
通讯作者：
Keni Qiu
中科院分区：
文献类型：
--
作者：
Yuanhui Ni;Zhiyao Gong;Weiwen Chen;Chengmo Yang;Keni Qiu
多级单元自旋转移矩随机存取存储器（MLC STT-RAM）是一种很有前途的非易失性存储器技术，用于构建寄存器，具有抗电磁辐射的天然抗辐射能力。与传统的基于SRAM的寄存器不同，由于硬磁畴和软磁畴的磁化方向无法独立翻转，因此MLC STT-RAM表现出不平衡的写入状态转换。该特征导致写状态在延迟和能量方面的不均匀成本。然而，当前的SRAM目标寄存器分配没有清楚地理解不同的写状态转换成本的影响。因此，这些方法在不考虑MLC STT-RAM所施加的溢出优先级的情况下试探性地选择要溢出的变量。针对这一局限性，本文提出了一种状态转移感知溢出成本最小化（SSCM）策略，以节省功耗时，MLC STT-RAM在寄存器设计。具体地说，首先根据不同状态转换频率的线性组合构建溢出成本模型。在该代价模型的指导下，编译器选择溢出的候选项，以实现更低的功耗和更高的性能。实验结果表明，所提出的SSCM技术可以节省19.4%的能量，提高了23.2%的寿命的MLC STT-RAM为基础的寄存器设计。
Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register design.
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DOI：
10.1016/j.vlsi.2016.01.003
发表时间：
2016-06
期刊：
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影响因子：
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作者：
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DOI：
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DOI：
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DOI：
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发表时间：
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期刊：
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影响因子：
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作者：
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