A wide-range and fast-locking all digital SARDLL for DVFS SoCs
A wide-range and fast-locking all digital SARDLL for DVFS SoCs
复制标题
适用于 DVFS SoC 的宽范围且快速锁定的全数字 SARDLL
DOI：
10.1587/elex.12.20150284
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发表时间：
2015-06
影响因子：
0.8
通讯作者：
Cai ZK
中科院分区：
文献类型：
--
作者：
Xu Tai-Long;Gao Xian-He;Hu Xue-You;Zha Chang-Jun;Xue Feng;Cai Zhi-Kuang;Xu Yu-Feng;Chen Jun-Ning;Cai ZK
: A wide-range and fast-locking all digital successive approximation register-controlled delay-locked loop (SARDLL) is presented for dynamic voltage / frequency scaling (DVFS) system-on-chips (SoCs). The proposed SARDLL eliminates the harmonic lock problem and zero-delay trap problem by using the improved resettable digitally controlled delay line (DCDL) and shortens the lock time by adopting the 2-b successive-approx-imation-register (SAR) algorithm. The proposed 6-bit SARDLL is designed using the TSMC 65 nm CMOS low power cell library. The layout ’ s active area is 91 µm × 91 µm. The post-layout simulation results show that the proposed SARDLL can operate from 250 MHz to 2 GHz. Its lock time is constant 9 cycles of the input clock. The power consumption is estimated to be 0.72 mW at 1.2 V supply voltage and 2-GHz clock frequency.
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DOI：
10.1109/tvlsi.2011.2182216
发表时间：
2013-02
影响因子：
2.8
作者：
You-Gang Chen;H. Tsao;Chorng-Sii Hwang
通讯作者：
You-Gang Chen;H. Tsao;Chorng-Sii Hwang
DOI：
10.1109/icm.2010.5696179
发表时间：
2010-12
期刊：
2010 International Conference on Microelectronics
影响因子：
--
作者：
Al-Hussein A. El-Shafie;S.E.-D. Habib
通讯作者：
Al-Hussein A. El-Shafie;S.E.-D. Habib
影响因子：
5.4
作者：
Rong-Jyi Yang;Shen-Iuan Liu
通讯作者：
Rong-Jyi Yang;Shen-Iuan Liu
DOI：
10.1109/tvlsi.2014.2336851
发表时间：
2015-07
影响因子：
2.8
作者：
Jian Yao;Zuochang Ye;Yan Wang
通讯作者：
Jian Yao;Zuochang Ye;Yan Wang
DOI：
10.1109/vldi-dat.2013.6533870
发表时间：
2013-04
期刊：
2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)
影响因子：
--
作者：
Chia-Yu Yao;Yung-Hsiang Ho
通讯作者：
Chia-Yu Yao;Yung-Hsiang Ho