An Expert System for Layout Generation

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The research is on a prototype expert system for layout generation in a hierarchial VLSI system. It applies a combination of rule-based and algorithmic-based techniques to a new layout style. Initial tests on a set of simple benchmarks have demonstrated the superiority of this expert system over various standard cell systems and its competitiveness with the human designer in terms of layout quality. Further research seeks to understand the full potential of this idea and develop a new design methodology that may replace the standard-cell design method. Specific research is in four areas: (1) adapt the prototype system so that it can use user-defined sizes of transistors and gates in the input description; (2) revise the strategy of knowledge representation so as to permit rules to be divided into smaller sets, and investigate the types of rules in a set as well as the granularity of the sets and the order in which they are applied; (3) study the problem of translation of symbolic to geometric representation with local restructuring using knowledge of the circuit functionality and the global floor plan; and (4) collect an extensive set of benchmarks for comparing layouts generated by different systems, and develop methods of comparison of layout quality.