RIA: System-Level Partitioning of VLSI Circuits Using DesignEvaluators

RIA：使用 DesignEvaluators 对 VLSI 电路进行系统级划分

• 批准号: 8909677
• 负责人: Fadi Kurdahi
• 金额: $ 7.77万
• 依托单位: University of California-Irvine
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1989
• 资助国家: 美国
• 起止时间: 1989-07-01 至 1992-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8909677&HistoricalAwards=false
• 关键词: RIA; System; Level; Partitioning; VLSI

This research is on automation of the system level partitioning problem. In particular it addresses the task of partitioning a design so as to minimize the number of VLSI chips, while still satisfying constraints on system performance and chip parameters. The P.I. is generalizing a model for area estimation for standard cell chips to handle other layout design styles. This model plays a central role in developing system level partitioning tools by providing accurate estimates of the design layout areas. Complimentary tools which evaluate other aspects and merits of the design, such as power consumption, performance and pin count are being developed. The tools are being integrated into a spreadsheet-like design aid which will allow the designer to interact with the system. This research investigates system level partitioning of a design so as to optimize system design with respect to many parameters. The P.I. has novel ideas, which show promise in solving this complex problem. The principal investigator is a promising and competent young professor who should make significant contributions to the field.

本文研究的是系统级划分的自动化 问题. 特别是它解决了划分设计的任务 以便最小化VLSI芯片的数量，同时仍然满足 对系统性能和芯片参数的限制。 私家侦探是 将用于标准单元芯片的面积估计的模型推广到 处理其他布局设计样式。 该模型在以下方面发挥着核心作用： 开发系统级分区工具， 设计布局面积的估算。 免费工具， 评估设计的其他方面和优点，例如功率 功耗、性能和引脚数正在开发中。 的工具 正在被集成到一个类似电子表格的设计辅助工具中， 让设计师与系统互动。 本研究调查了设计的系统级划分， 以优化系统设计的许多参数。 私家侦探 有新颖的想法，在解决这一复杂问题方面显示出希望。 首席研究员是一位有前途、有能力的年轻教授 他们应该为这个领域做出重大贡献。