RIA: System-Level Partitioning of VLSI Circuits Using DesignEvaluators

这项研究是关于系统级分区问题的自动化。 特别是，它解决了设计分区的任务，以最大限度地减少 VLSI 芯片的数量，同时仍然满足系统性能和芯片参数的约束。 P.I.正在推广标准单元芯片面积估计模型，以处理其他布局设计风格。 该模型通过提供设计布局区域的准确估计，在开发系统级分区工具中发挥着核心作用。 正在开发评估设计的其他方面和优点（例如功耗、性能和引脚数）的免费工具。 这些工具正在被集成到类似电子表格的设计辅助工具中，这将允许设计人员与系统进行交互。 这项研究调查了设计的系统级划分，以便针对许多参数优化系统设计。 P.I. 有新颖的想法，有望解决这个复杂的问题。 首席研究员是一位有前途、有能力的年轻教授，应该对该领域做出重大贡献。

This research is on automation of the system level partitioning problem. In particular it addresses the task of partitioning a design so as to minimize the number of VLSI chips, while still satisfying constraints on system performance and chip parameters. The P.I. is generalizing a model for area estimation for standard cell chips to handle other layout design styles. This model plays a central role in developing system level partitioning tools by providing accurate estimates of the design layout areas. Complimentary tools which evaluate other aspects and merits of the design, such as power consumption, performance and pin count are being developed. The tools are being integrated into a spreadsheet-like design aid which will allow the designer to interact with the system. This research investigates system level partitioning of a design so as to optimize system design with respect to many parameters. The P.I. has novel ideas, which show promise in solving this complex problem. The principal investigator is a promising and competent young professor who should make significant contributions to the field.