Collaborative Research: EAGER: IC-Cloak: Integrated Circuit Cloaking against Reverse Engineering

合作研究：EAGER：IC-Cloak：针对逆向工程的集成电路隐形

• 批准号: 2213486
• 负责人: Fadi Kurdahi
• 金额: $ 10万
• 依托单位: University of California-Irvine
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-05-15 至 2025-04-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2213486&HistoricalAwards=false
• 关键词: Collaborative; Research; EAGER; IC; Cloak

Outsourcing the design and manufacturing of integrated circuits (ICs) has minimized the operating and maintenance costs for a plethora of electronic design companies with reduced time-to-market. However, such outsourcing and benefits lead to complex verification of the fabricated ICs. Additionally, the security threats in terms of reverse engineering the design have surfaced. To address such reverse engineering of ICs, this project proposes insertion of noise in the IC layout that minimizes the probability of success in IC reverse engineering. The insertion of noise must also meet the standard IC design flow requirements and pass the verification and validation. To achieve this goal, this project integrates the adversarial machine learning with the IC design flow to enable efficient IC design protection despite attacker obtaining the scanning electron microscope (SEM)/layout images of a given IC. In the first phase, the project develops a surrogate machine learning model to detect the gates in SEM images, followed by incubation of novel adversarial perturbations under spatial constraints on the SEM images. The perturbations obtained through the adversarial learning will be evaluated and embedded in some of the available open-source standard cell libraries, guaranteeing compatibility with existing IC design flow tools. Successful completion of the project will result in a suite of secure IC cell libraries that are compatible with IC design flows. Specifically, this project (i) develops novel IC cell layouts that cannot be identified by an adversary despite obtaining the images through reverse engineering; (ii) introduces novel adversarial perturbation generation under spatial constraints. Due to the interdisciplinary nature, the outcome of the project impacts a broad variety of researchers in the domains of IC design and adversarial machine learning. The development of library cells from this project will be outsourced with relevant licenses to academia and industry. The project is expected to generated multiple types of data including IC layouts, SEM images, and cell models. All the codes will be written using Python, and SystemC/Verilog (If required). Fully functional and tested codes will be documented and will be made available through GitHub. The website of PIs (http://mymason.gmu.edu/~spudukot) will add a new page for downloading the source codes. Data will be retained at GMU, UC Davis, and UC Irvine for a minimum of three years after conclusion of the award. Data related to students’ research work will be retained for four years after the degree is awarded.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

将集成电路(IC)的设计和制造外包，使大量电子设计公司的运营和维护成本降至最低，并缩短了上市时间。然而，这种外包和好处导致了对已制造IC的复杂验证。此外，逆向工程设计方面的安全威胁已经浮出水面。为了解决IC的这种逆向工程，本项目提出在IC版图中插入噪声，以最大限度地降低IC逆向工程的成功概率。噪声的插入还必须满足标准的IC设计流程要求，并通过验证和验证。为了实现这一目标，该项目将对抗性机器学习与IC设计流程相结合，以实现高效的IC设计保护，尽管攻击者获得了给定IC的扫描电子显微镜(SEM)/版图图像。在第一阶段，该项目开发了一个代理机器学习模型来检测扫描电子显微镜图像中的门，然后在扫描电子显微镜图像上孵化空间约束下的新的对抗性扰动。通过对抗性学习获得的扰动将被评估并嵌入到一些可用的开源标准单元库中，以保证与现有IC设计流程工具的兼容性。该项目的成功完成将产生一套与IC设计流程兼容的安全IC单元库。具体地说，这个项目(I)开发了新的IC单元布局，尽管通过逆向工程获得了图像，但对手无法识别这些布局；(Ii)引入了空间约束下的新的对抗性扰动生成。由于跨学科的性质，该项目的结果影响了IC设计和对抗性机器学习领域的广泛研究人员。来自该项目的图书馆细胞的开发将与学术界和工业界的相关许可证一起外包。该项目预计将产生多种类型的数据，包括集成电路版图、扫描电子显微镜图像和单元模型。所有代码都将使用Python和SystemC/Verilog(如果需要)编写。完整的功能和经过测试的代码将被记录在案，并将通过GitHub提供。PI(http://mymason.gmu.edu/~spudukot))网站将增加一个下载源代码的新页面。数据将在GMU、加州大学戴维斯分校和加州大学欧文分校在奖项结束后保留至少三年。与学生研究工作相关的数据将在学位授予后保留四年。这一奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse Engineering

CAPTIVE：限制对抗性扰动以阻止 IC 逆向工程

• DOI: 10.3390/info14120656
• 发表时间: 2023
• 期刊: Information
• 影响因子: 3.1
• 作者: Zargari, Amir Hosein;AshrafiAmiri, Marzieh;Seo, Minjun;Pudukotai Dinakarrao, Sai Manoj;Fouda, Mohammed E.;Kurdahi, Fadi
• 通讯作者: Kurdahi, Fadi