ITR: Synthesis of Adaptive Mission-Specific Processors

该项目的目标是为基于欧文加州大学开发的Morphosys体系结构的特定任务处理器(MSP)的自动综合开发设计方法、软件工具和编程环境。由于其硬件设计不是针对应用(S)量身定做的，通用的嵌入式处理器体系结构使得面积和功耗的使用效率低下。另一方面，ASIC不能被更新以适应不同的算法改进。通过允许一组目标应用程序来规定体系结构，MSP设计结合了必要的组件和互连，以优化特定程序套件的性能。合成的体系结构是动态可重新配置的，并且支持可重定向的编译器以结合算法增强或改变任务规范。所提出的方法依赖于将用高级算法语言表达的程序编译成数据流图(DFG)格式，并从该格式编译成VHDL语言。这项技术是作为科罗拉多州立大学卡梅隆项目的一部分开发的。将开发一个新的MSP设计框架，以纳入基于约束的MSP综合和估计以及对综合架构的编译支持。

The objective of this project is to develop the design methodology, software tools and programming environment for the automated synthesis of Mission-specific Processors (MSPs) based on the Morphosys architecture developed at UC, Irvine. Because their hardware design is not tailored to the application(s), generic embedded processor architectures make inefficient use of area and power. ASICs on the other hand cannot be updated to accommodate different algorithm improvements. By allowing a set of target applications to dictate the architecture, MSP designs incorporate the necessary components and interconnections to optimize the performance of a specific suite of programs. The synthesized architecture is dynamically reconfigurable and supports a retargetable compiler to incorporate algorithm enhancements or changing task specifications. The proposed approach relies on the compilation of a program expressed in a high-level algorithmic language into a data-flow graph (DFG) format and from that format into VHDL. This technology has been developed as part of the Cameron Project at Colorado State University. A new MSP design framework will be developed to incorporate constraint-based MSP synthesis and estimation as well as compilation support for the synthesized architecture.