RIA: Accurate Timing Models for Verification and Test of High Performance MOS and Bipolar Technologies

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The research is on a methodology for efficiently analyzing high performance MOS and bipolar circuits but with capabilities for predicting the analog behavior. Prototype software is being developed for analyzing logic path delays. The algorithms are based in the asymptotic waveform evaluation (AWE) method which enables the analysis of general RLC interconnect models. The AWE capabilities are being used to develop a waveform analyzer for high speed bipolar and MOS logic gate and interconnect models. Specific topics being investigated are a. evaluating the logic stage waveforms, b. developing gate delay models for both technologies, c. modeling the coupling between logic states, d. statistical waveform analysis, and e. analyzing deformed logic stage models.