PYI: CAD Tools for New Circuit Technologies

该研究致力于开发系统级的仿真能力，使其与芯片级的仿真能力一样强大。为此，正在开发适用于集成电路、封装、模块和电路板级别而又不失通用性的工具。正在研究的具体领域是：快速提取技术，以一些准确性换取效率；以及实现自顶向下设计的仿真模型和技术。电路板或多芯片模块的时序分析需要开发用于在系统仿真级别提取、表征和模拟传输线的工具。为此，正在探索与片上RC互连电路相似的互连宏观模型，这些模型与系统级设计自动化工具兼容。

Pillage The research is on developing simulation capabilities at the system level, which are as powerful as those at the chip level. To this end, tools which are applicable at the integrated circuit, packaging, module, and board levels without loss of generality are being developed. Specific areas being investigated are: fast extraction techniques which trade off some accuracy for efficiency; and simulation models and techniques to enable topdown design. Timing analysis of boards or multi-chip modules requires development of tools for the extraction, characterization and simulation of transmission lines at the system simulation level. Toward this end interconnect macro- models, similar to those for on-chip RC interconnect circuits, which are compatible with system-level design automation tools, are being explored.