RIA: Fault Tolerance in Analog VLSI Focal Plane Processors

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Andreou Analog VLSI is a promising approach to the design of systems for machine vision since it leads to distributed, data driven architectures, that map the light stimuli directly to the crux of computing hardware, the silicon substrate. This emerging class of signal processing systems is based on relatively simple computational primitives such as logarithmic photodetectors, aggregating resistive networks and coupled non-linear resistive networks. Furthermore, there are power and area efficient features that make them attractive for wafer scale integration. However, manufacturing of such systems at the wafer scale will strongly depend on establishing design methodologies that make them robust to defects in the fabrication process. Equally important, these must be augmented with yield estimation models as well as testing and failure analysis procedures. The above issues are addressed in this research in a comprehensive program that involves both analytical calculations and experimental studies.