RIA: Fault Tolerance in Analog VLSI Focal Plane Processors

Andreou Analog VLSI是一种很有前途的机器视觉系统设计方法，因为它导致分布式、数据驱动的架构，将光刺激直接映射到计算硬件的关键——硅衬底。这种新兴的信号处理系统基于相对简单的计算基元，如对数光电探测器、聚合电阻网络和耦合非线性电阻网络。此外，它们具有功率和面积效率高的特点，使其对晶圆规模集成具有吸引力。然而，这种系统在晶圆规模上的制造将强烈依赖于建立设计方法，使它们对制造过程中的缺陷具有鲁棒性。同样重要的是，这些必须与产量估计模型以及测试和失效分析程序相结合。上述问题在本研究中以一个综合的方案来解决，包括分析计算和实验研究。

Andreou Analog VLSI is a promising approach to the design of systems for machine vision since it leads to distributed, data driven architectures, that map the light stimuli directly to the crux of computing hardware, the silicon substrate. This emerging class of signal processing systems is based on relatively simple computational primitives such as logarithmic photodetectors, aggregating resistive networks and coupled non-linear resistive networks. Furthermore, there are power and area efficient features that make them attractive for wafer scale integration. However, manufacturing of such systems at the wafer scale will strongly depend on establishing design methodologies that make them robust to defects in the fabrication process. Equally important, these must be augmented with yield estimation models as well as testing and failure analysis procedures. The above issues are addressed in this research in a comprehensive program that involves both analytical calculations and experimental studies.