Analog Computation and VLSI Architectures for Contraction Mappings

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9313934 Andreou This project will attempt to develop a new class of recurrent networks. The architecture of the networks is inspired by recent work on image encoding based on iterated transformation theory and it's associated inverse problems. The PIs purpose to restrict our investigation to networks that can be physically implemented in subthreshold analog VLSI. With their approach analog components that implement high quality arithmetic operations are unnecessary. Indeed, significant departures from ideal linear behavior can be tolerated, provided that these departures are reproducible across chips. As a concrete application they will consider that task of data compression and decompression. Compression is accomplished by the relaxation of an electronic circuit to a steady state while compression is preformed either off-line or with an adaptive analog VLSI neural network architecture. For hardware compression they propose to use a learning algorithm that learns both the weight and the connection topology. Hence, the ability to gate and switch electrical current is central to the operation of these networks. The main thrust of this investigation is to design and characterize the circuits that implement the required transformations in one dimension. A successful outcome to this investigation has the potential for making compression and decompression technology available for all low-power applications. ***