CRII: SaTC: RUI: When Logic Locking Meets Hardware Trojan Mitigation and Fault Tolerance

硬件漏洞的巨大后果，包括修复这些漏洞的昂贵前景，一直是数十份国家报告的主题。该项目旨在解决这些日益严重的问题。特别是，该项目的新奇在于基于现实攻击模型下的可重构性概念和不同硬件安全要求的统一定义来概念化硬件安全性和可靠性。该项目更广泛的意义和重要性包括帮助国家电子行业保护基础硬件，以实现可信赖的信息时代，并增加寻求科学和工程专业本科和研究生学位的少数民族人数，重点是网络安全。在无晶圆厂范式中，集成电路设计公司不仅必须设想传统的容错技术，以降低更换有缺陷组件的成本，而且还包括避免盗版和过度生产其设计以及减轻由不可信的代工厂潜在插入的硬件特洛伊木马的过程。在这个项目中，研究人员和他的团队专注于两个阶段的全面硬件安全性和可靠性框架。首先，研究团队研究了安全的嵌入式现场可编程门阵列（eFPGA）编辑解决方案。eFPGA的结构可以提供机会，使集成电路不仅可以抵御逻辑锁定攻击，还可以减少硬件木马并容忍运行时的故障。其次，研究小组提出了具有多级激活和功能阶段的动态密钥方案，以提供高度的逻辑锁定安全性，硬件特洛伊木马缓解和容错，而不会显著增加面积和功耗。该项目的成果将传播到备受推崇的设计自动化场所，并将发布一个开源计算机程序，该程序将接收高效的数字电路，并输出一个低开销和可证明安全的网表，考虑不同的硬件安全要求。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The enormous consequences of hardware vulnerabilities, including the costly prospect of fixing them, have been the subject of dozens of national reports. This project aims to address these growing issues. Particularly, the project’s novelty is conceptualizing hardware security and reliability based on the notion of reconfigurability under realistic attack models and a unified definition of different hardware security requirements. The project's broader significance and importance include helping the national electronics industry safeguard the underlying hardware for a trustworthy information age and increasing the number of minorities seeking undergraduate and graduate degrees in science and engineering, with a focus on cybersecurity.In a fabless paradigm, integrated circuit design houses must envision not only traditional fault-tolerance techniques to reduce the cost of replacing defective components, but also procedures to avoid piracy and overproduction of their designs as well as mitigate potentially inserted hardware Trojans by untrusted foundries. In this project, the investigator and his team focus on a comprehensive hardware security and reliability framework in two phases. First, the research team investigates secure embedded Field-Programmable Gate Array (eFPGA) redaction solutions. The structure of eFPGAs can provide opportunities to make the integrated circuits secure not just against logic locking attacks but also to mitigate hardware Trojans and tolerate faults at run-time. Second, the research team propose dynamic key schemes with multi-level activation and functional stages to offer a high degree of logic locking security, hardware Trojan mitigation, and fault tolerance without significantly imposing area and power overheads. The outcomes of this project will be disseminated to well-respected design automation venues, and an open-source computer program will be released that receives an efficient digital circuit and outputs a low-overhead and provably secure netlist considering different hardware security requirements. This will help the national high-tech industry thrive and contribute to economic prosperity, innovation, and security.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.