Emulations among Processor Arrays: A Theoretical Study

处理器阵列之间的仿真：理论研究

• 批准号: 9013184
• 负责人: Arnold Rosenberg
• 金额: $ 15.79万
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1991
• 资助国家: 美国
• 起止时间: 1991-02-01 至 1994-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9013184&HistoricalAwards=false
• 关键词: Emulations; among; Processor; Arrays; Theoretical

The research project combines work on graph embeddings and parallel algorithms to study a variety of emulation problems for processor arrays, i.e., parallel architectures that consist of a communication network having processing elements at each mode. The research focuses on a variey of theoretical problems that relate to the design, programming, and implementation of "real" processor arrays. More specifically, the research problems motivating the research include attempts to: o simplify the programming of a parallel architecture, by allowing the programmer to specify an algorithm for an idealized architecture which is then emulated by an actual architecture; o understand the relative communication power of various interconnection networks, by determining how efficiently arrays based on each of the networks can emulate arrays based on the others, on general computations; o achieve fault tolerance, by having an array that has been crippled by defects emulate a fault-free version of itself. The theoretical results obtained in the course of the proposed research should lend insights into the "real" analogs of the problems studied.

该研究项目结合了图嵌入和并行算法的工作，以研究处理器阵列的各种仿真问题，即并行架构，由每个模式都具有处理元素的通信网络组成。该研究的重点是与“真实”处理器阵列的设计、编程和实现相关的各种理论问题。更具体地说，激励本研究的研究问题包括：O简化并行架构的编程，允许程序员为理想架构指定算法，然后由实际架构模拟；通过确定基于每个网络的阵列如何有效地模拟基于其他网络的阵列，在一般计算上，了解各种互连网络的相对通信能力；通过让一个被缺陷破坏的数组模拟其自身的无故障版本来实现容错。在拟议的研究过程中获得的理论结果应该有助于对所研究问题的“真实”类似物的见解。