Parallel Architecture: Design, Validation, Implementation

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This project is a program of research on theoretical aspects of the design cycle for a special genre parallel architectures, namely, multipurpose arrays of identical processing elements (arrays, for short). The first phase of the program will concern itself with issues concerning the design of arrays, concentrating on questions concerning the relative computational efficiency gained by incorporating a variety of structural features into the design. As but one example, what are the relative merits of point to point communication vs. communication via shared memories vs. communication via (reconfigurable) busses? The main vehicle for this phase will be studies of the intersimulatability of architectures. The second phase of the program will concentrate on the problem of validating a proposed multipurpose architecture by demonstrating its ability to handle a variety of classes of computational tasks efficiently. The main vehicle for this will be an enhanced version of the logical mapping problem for parallel architectures. The final phase of the program will be concerned with the physical implementation of the proposed architecture, focusing on issues such as fault-tolerance and efficient implementability in physical space. One major tool in this phase will be the new notion of the physical mapping problem for parallel architectures. Throughout, our measures of efficiency will include delay, resource utilization, and load balancing; and, we shall consider a variety of modes of parallel computation, viewing SIMD and MIMD as the extremes in the spectrum of modes.