Parallel Architecture: Design, Validation, Implementation

本项目是一个研究特殊类型并行架构设计周期理论方面的项目，即相同处理元素的多用途阵列（简称阵列）。该计划的第一阶段将关注与阵列设计有关的问题，重点关注通过将各种结构特征纳入设计而获得的相对计算效率问题。举个例子，点对点通信vs.通过共享存储器通信vs.通过（可重构）总线通信的相对优点是什么？这一阶段的主要载体将是研究体系结构的可互模拟性。该计划的第二阶段将集中在验证提议的多用途架构的问题上，通过展示其有效处理各种类型的计算任务的能力。这方面的主要工具将是并行体系结构逻辑映射问题的增强版本。该计划的最后阶段将关注拟议体系结构的物理实现，重点关注物理空间中的容错和有效可实现性等问题。这个阶段的一个主要工具将是并行架构的物理映射问题的新概念。在整个过程中，我们的效率度量将包括延迟、资源利用率和负载平衡；并且，我们将考虑各种并行计算模式，将SIMD和MIMD视为模式谱中的极端。

This project is a program of research on theoretical aspects of the design cycle for a special genre parallel architectures, namely, multipurpose arrays of identical processing elements (arrays, for short). The first phase of the program will concern itself with issues concerning the design of arrays, concentrating on questions concerning the relative computational efficiency gained by incorporating a variety of structural features into the design. As but one example, what are the relative merits of point to point communication vs. communication via shared memories vs. communication via (reconfigurable) busses? The main vehicle for this phase will be studies of the intersimulatability of architectures. The second phase of the program will concentrate on the problem of validating a proposed multipurpose architecture by demonstrating its ability to handle a variety of classes of computational tasks efficiently. The main vehicle for this will be an enhanced version of the logical mapping problem for parallel architectures. The final phase of the program will be concerned with the physical implementation of the proposed architecture, focusing on issues such as fault-tolerance and efficient implementability in physical space. One major tool in this phase will be the new notion of the physical mapping problem for parallel architectures. Throughout, our measures of efficiency will include delay, resource utilization, and load balancing; and, we shall consider a variety of modes of parallel computation, viewing SIMD and MIMD as the extremes in the spectrum of modes.