Compilation and Design for Parallel Computer Architectures

SIMD（单指令流，多数据流）和VLIW（非常 长指令字）体系结构已成功地作为目标 对于并行化编译器来说，很大程度上是因为它们解决了 在编译时静态同步，产生零运行时 进程间同步的成本。 然而，由于SIMD和 VLIW机器只支持单个控制流线程，它们不能 执行不同的循环、条件语句、子例程调用，或 甚至是并行的可变时间指令。 因此，许多方案 必须忽略并行性，并且由此产生的代码序列化 会大大降低加速和效率。 最近，一个新的 称为屏障MIMD（多指令）的体系结构 流，多数据流）体系结构已经作为 一种新的并行MIMD结构，它可以保持静态调度 SIMD和VLIW的优点，而且几乎可以并行执行任何 程序设计语言构造 结果是， 并行化可以利用大量的程序并行性 编译器，并有效地执行屏障MIMD。 的目标 本项目旨在改进和提高编译器技术 能够利用屏障MIMD硬件。 指令和数据 利用静态编译时知识的存储器硬件设计 为了显著提高势垒MIMD性能， 研究了

SIMD (Single Instruction stream, Multiple Data stream) and VLIW (Very Long Instruction Word) architectures have been successful as targets for parallelizing compilers in large part because they resolve synchronizations statically, at compile-time, yielding zero run-time cost for synchronization between processes. However, since SIMD and VLIW machines support only a single control flow thread, they cannot execute distinct loops, conditional statements, subroutine calls, nor even variable-time-instructions in parallel. Hence, much program parallelism must be ignored, and the resulting serialization of code can dramatically reduce speedup and efficiency. Recently, a new architecture called barrier MIMD (Multiple Instruction stream, Multiple Data stream) architectures has been introduced as a new parallel MIMD architecture that can retain the static scheduling advantages of SIMD and VLIW, but also execute in parallel almost any programming language construct. The result is that a far larger amount of program parallelism can be exploited by a parallelizing compiler and efficiently executed on a barrier MIMD. The objective of this project is to improve and advance the compiler technology capable of exploiting barrier MIMD hardware. Instruction and data memory hardware designs which exploit static, compile-time knowledge to dramatically increase barrier MIMD performance will also be investigated.