Compilation and Design for Parallel Computer Architectures

SIMD（单指令流，多数据流）和VLIW（超长指令字）架构已经成功地成为并行化编译器的目标，这在很大程度上是因为它们在编译时静态地解决同步问题，为进程之间的同步产生零运行时成本。但是，由于SIMD和VLIW机器只支持单个控制流线程，因此它们不能并行执行不同的循环、条件语句、子例程调用，甚至不能并行执行可变时间指令。因此，许多程序的并行性必须被忽略，而由此产生的代码序列化会大大降低加速和效率。最近，一种新的多指令流、多数据流（barrier MIMD）架构作为一种新的并行MIMD架构被引入，它既保留了SIMD和VLIW的静态调度优势，又可以并行执行几乎任何编程语言结构。其结果是，并行化编译器可以利用大量的程序并行性，并在屏障MIMD上有效地执行。该项目的目标是改进和推进能够利用屏障MIMD硬件的编译器技术。指令和数据存储硬件设计利用静态，编译时的知识，以显着提高屏障MIMD性能也将进行研究。

SIMD (Single Instruction stream, Multiple Data stream) and VLIW (Very Long Instruction Word) architectures have been successful as targets for parallelizing compilers in large part because they resolve synchronizations statically, at compile-time, yielding zero run-time cost for synchronization between processes. However, since SIMD and VLIW machines support only a single control flow thread, they cannot execute distinct loops, conditional statements, subroutine calls, nor even variable-time-instructions in parallel. Hence, much program parallelism must be ignored, and the resulting serialization of code can dramatically reduce speedup and efficiency. Recently, a new architecture called barrier MIMD (Multiple Instruction stream, Multiple Data stream) architectures has been introduced as a new parallel MIMD architecture that can retain the static scheduling advantages of SIMD and VLIW, but also execute in parallel almost any programming language construct. The result is that a far larger amount of program parallelism can be exploited by a parallelizing compiler and efficiently executed on a barrier MIMD. The objective of this project is to improve and advance the compiler technology capable of exploiting barrier MIMD hardware. Instruction and data memory hardware designs which exploit static, compile-time knowledge to dramatically increase barrier MIMD performance will also be investigated.