Topological and Physical Layout Design Techniques for Yield Enhancement

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Koren This research is on design tools which can compensate for manufacturing yield losses due to the complexity of the logic. Preliminary results have shown that yield can be enhanced by the technique of reducing the sensitivity of the chip to point defects. Yield optimization algorithms and techniques which are applicable to the last two stages of design - topological/symbolic, and physical layout are being explored. Physical layout strategies for yield enhancement in the channel routing and compaction phases for standard cell designs are being investigated. Yield enhancements in topological designs are being illustrated through PLA-based designs.