Improving the Performance of Scalable Shared-Memory Multiprocessors

过去四年在Cedar多处理器系统上开发的复杂性能测量和仿真工具被用于研究几个关键的体系结构和编译器问题，这些问题可以增强可扩展共享内存多处理器的性能。这些问题包括内存延迟减少和隐藏策略、循环级并行性的数据同步要求以及分层网络设计。对这些问题的研究涉及硬件辅助的雪松经验数据收集和模拟的使用。由此获得的信息可能导致下一代系统的设计，与目前的系统相比，在更广泛的应用范围内提供更高的持续性能。

Yew Sophisticated performance measurement and simulation tools developed on the Cedar multiprocessor system during the last four years are being used to study several key architectural and compiler issues that can enhance the performance of scalable shared memory multiprocessors. These issues include memory latency reduction and hiding strategies, data synchronization requirements for loop-level parallelism, and hierarchical network design. The study of these issues involves the hardware-assisted collection of empirical data on Cedar and the use of simulation. The information thus obtained could lead to the design of next- generation systems that, compared to present-day systems, provide higher sustained performance across a broader range of applications.