RIA: Partitioning of VLSI Systems for Distributed Simulation

RIA：用于分布式仿真的 VLSI 系统分区

• 批准号: 9309658
• 负责人: Roger Chamberlain
• 金额: $ 9万
• 依托单位: Washington University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1993
• 资助国家: 美国
• 起止时间: 1993-07-01 至 1996-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9309658&HistoricalAwards=false
• 关键词: RIA; Partitioning; VLSI; Systems; Distributed

Chamberlain This research is on approaches to partitioning VLSI systems for distributed simulation on multiprocessor architectures. The approach is to use knowledge of a VLSI system and the distributed simulation algorithms to perform a partitioning and assignment of system components to processors in a manner that minimizes the execution time of the distributed simulation. Central to the approach is an initial partitioning that is refined as information is gathered about the simulation workload. In this way assignment of components to processors can take advantage of measured data that is unknown (and therefore unavailable) prior to the simulation run. The approach has three phases: 1. Algorithms for initial partitioning of the circuit components are being developed; 2. Means of assigning partitions to processors are being developed; and 3. Rules for migrating components from one processor to another are being devised.

本研究是关于在多处理器架构上为分布式仿真划分VLSI系统的方法。该方法是利用超大规模集成电路系统的知识和分布式仿真算法，以最小化分布式仿真的执行时间的方式执行系统组件的分区和分配给处理器。该方法的核心是初始分区，随着收集有关模拟工作负载的信息，对其进行细化。通过这种方式，将组件分配给处理器可以利用在模拟运行之前未知（因此不可用）的测量数据。该方法分为三个阶段：1。正在开发用于电路元件初始划分的算法；2. 正在开发将分区分配给处理器的方法；和3。将组件从一个处理器迁移到另一个处理器的规则正在被设计出来。