RIA: Partitioning of VLSI Systems for Distributed Simulation

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Chamberlain This research is on approaches to partitioning VLSI systems for distributed simulation on multiprocessor architectures. The approach is to use knowledge of a VLSI system and the distributed simulation algorithms to perform a partitioning and assignment of system components to processors in a manner that minimizes the execution time of the distributed simulation. Central to the approach is an initial partitioning that is refined as information is gathered about the simulation workload. In this way assignment of components to processors can take advantage of measured data that is unknown (and therefore unavailable) prior to the simulation run. The approach has three phases: 1. Algorithms for initial partitioning of the circuit components are being developed; 2. Means of assigning partitions to processors are being developed; and 3. Rules for migrating components from one processor to another are being devised.