CSR: Small: Concurrent Accelerated Data Integration

CSR：小型：并发加速数据集成

• 批准号: 1527510
• 负责人: Roger Chamberlain
• 金额: $ 50.22万
• 依托单位: Washington University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-10-01 至 2019-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1527510&HistoricalAwards=false
• 关键词: CSR; Small; Concurrent; Accelerated; Data

Not only is big data voluminous, it is varied. Individual data analysis tasks must first collect data sets that are often in unrelated locations and frequently in vastly disparate formats. These data sets almost always need multiple changes prior to the analysis task, such as format normalization, data cleansing, type checking, and outlier detection. These "data integration" activities typically consume an inordinate amount of time and effort both on the part of the data analyst and on the part of the computing systems.This project is to design, prototype, and evaluate an Application-Specific Instruction Processor (ASIP) that will support the concurrent execution of data integration workloads for multiple streams of big data. The ASIP will not only execute an individual integration stream, but will be capable of concurrently executing a number of distinct data integration streams (each with its own processing requirements), enabling data from disparate sources to be utilized for analysis. Successful ASIP deployment will substantially increase the throughput (and therefore effectiveness) of big data analysis across a range of fields.What is unique about the ASIP design is not just that the instruction set will be customized, but the entire data path will be optimized for the data integration problem. Both very long instruction word (VLIW) and vector techniques will be used to expose and exploit parallelism. Complex transformations will be supported by a combination of customized engines as well as hardware virtualization. The optimization for data integration not only includes the computational data path, but explicit attention will be paid to the memory subsystem design as well. The project will include super-optimization of memory subsystems from individual applications to the application class comprised of data integration workflows.The result should lead to dramatic improvements in the overhead of preparing data for analysis.

大数据不仅数量庞大，而且种类繁多。各个数据分析任务必须首先收集通常位于不相关位置且格式截然不同的数据集。这些数据集在分析任务之前几乎总是需要进行多次更改，例如格式规范化、数据清理、类型检查和异常值检测。这些“数据集成”活动通常会消耗数据分析师和计算系统大量的时间和精力。该项目旨在设计、原型化和评估特定于应用程序的指令处理器 (ASIP)，该处理器将支持多个大数据流的数据集成工作负载的并发执行。 ASIP 不仅会执行单个集成流，而且能够同时执行多个不同的数据集成流（每个数据集成流都有自己的处理要求），从而能够利用来自不同来源的数据进行分析。成功的ASIP部署将大幅提高多个领域大数据分析的吞吐量（从而提高效率）。ASIP设计的独特之处不仅在于指令集将被定制，而且整个数据路径将针对数据集成问题进行优化。超长指令字 (VLIW) 和向量技术都将用于公开和利用并行性。定制引擎和硬件虚拟化的组合将支持复杂的转换。数据集成的优化不仅包括计算数据路径，还将特别关注内存子系统的设计。 该项目将包括从单个应用程序到由数据集成工作流程组成的应用程序类的内存子系统的超级优化。其结果应该会导致准备分析数据的开销显着改善。

项目成果

Exploring Portability and Performance of OpenCL FPGA Kernels on Intel HARPv2

• DOI: 10.1145/3318170.3318180
• 发表时间: 2019-05
• 期刊: Proceedings of the International Workshop on OpenCL
• 作者: A. Cabrera;R. Chamberlain

Data Integration Tasks on Heterogeneous Systems Using OpenCL

使用 OpenCL 的异构系统上的数据集成任务

• DOI: 10.1145/3318170.3318187
• 发表时间: 2019
• 期刊: Proc. of 7th International Workshop on OpenCL
• 作者: Faber, Clayton J.;Cabrera, Anthony M.;Booker, Orondé;Maayan, Gabe;Chamberlain, Roger D.
• 通讯作者: Chamberlain, Roger D.