Architecture, Algorithms and Software in the Design of a Massively Parallel, Fine Grain Processor

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This project is investigating the design, implementation, and use of a family of family of massively parallel computers that use one processor per digit. A first generation design, completed in an earlier project, contains 16,384 fine grain processors on a single board. The processors contain a small number of parallel logic circuits and a configuration memory that controls the logic and interconnect. The entire machine is programmed for a problem by setting all configuration registers to transform the machine into a special-purpose computer for the problem. By improving the density of processors on chips and the speeds of interconnect and interface, this project is increasing the operation rate of the machine by a factor of 4 to 10. In addition to the design and implementation of architectures, this project is developing both high and low level programming tools for the machines. Finally, algorithms for solving compute intensive problems on these machines are being developed and tested.